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Wed, 24 Sep 2025 05:23:34 -0700 (PDT) Received: from [192.168.68.110] ([152.234.123.171]) by smtp.gmail.com with ESMTPSA id 00721157ae682-747ff308313sm29236287b3.37.2025.09.24.05.23.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Sep 2025 05:23:34 -0700 (PDT) Message-ID: Date: Wed, 24 Sep 2025 09:23:31 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 04/12] target/riscv: Record misa_ext in TCGTBCPUState.cs_base To: Richard Henderson , qemu-devel@nongnu.org Cc: Pierrick Bouvier , Alistair Francis , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org References: <20250923023922.3102471-1-richard.henderson@linaro.org> <20250923023922.3102471-5-richard.henderson@linaro.org> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20250923023922.3102471-5-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1130; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 9/22/25 11:39 PM, Richard Henderson wrote: > The tb_flush within write_misa was incorrect. It assumed > that we could adjust the ISA of the current processor and > discard all TB and all would be well. But MISA is per vcpu, > so globally flushing TB does not mean that the TB matches > the MISA of any given vcpu. > > By recording misa in the tb state, we ensure that the code > generated matches the vcpu. > > Reviewed-by: Pierrick Bouvier > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > Cc: Alistair Francis > Cc: Weiwei Li > Cc: Daniel Henrique Barboza > Cc: Liu Zhiwei > Cc: qemu-riscv@nongnu.org > --- > target/riscv/csr.c | 3 --- > target/riscv/tcg/tcg-cpu.c | 3 ++- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 8842e07a73..3c8989f522 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -25,7 +25,6 @@ > #include "pmu.h" > #include "time_helper.h" > #include "exec/cputlb.h" > -#include "exec/tb-flush.h" > #include "exec/icount.h" > #include "accel/tcg/getpc.h" > #include "qemu/guest-random.h" > @@ -2173,8 +2172,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, > env->mstatus &= ~MSTATUS_FS; > } > > - /* flush translation cache */ > - tb_flush(env_cpu(env)); > env->xl = riscv_cpu_mxl(env); > return RISCV_EXCP_NONE; > } > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 78fb279184..143ab079d4 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -191,7 +191,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) > > return (TCGTBCPUState){ > .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, > - .flags = flags > + .flags = flags, > + .cs_base = env->misa_ext, > }; > } >