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[84.0.19.134]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15e1289befsm636740266b.28.2026.07.13.03.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 03:00:35 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , Tvrtko Ursulin , Natalie Vock , Thorsten Leemhuis Subject: Re: [PATCH] drm/amd/pm/ci: Don't disable MCLK DPM on Bonaire 0x6658 (R7 260X) Date: Mon, 13 Jul 2026 12:00:33 +0200 Message-ID: In-Reply-To: References: <20260713061443.32561-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Monday, July 13, 2026 10:28:08=E2=80=AFAM Central European Summer Time T= horsten=20 Leemhuis wrote: > On 7/13/26 08:14, Timur Krist=C3=B3f wrote: > > The old radeon driver has a documented workaround in ci_dpm.c > > which claims that Bonaire 0x6658 with old memory controller > > firmware is unstable with MCLK DPM, so as a precaution I > > disabled MCLK DPM on this ASIC in amdgpu. > >=20 > > Note that the old MC firmware is not actually used with > > amdgpu, but in theory it's possible that the VBIOS sets > > up the ASIC with an old MC firmware that is already running > > when amdgpu initializes (in which case amdgpu doesn't > > load its own firmware). > >=20 > > What I expected to happen is that the GPU would simply use > > its maximum memory clock, and indeed this is what seemed > > to happen according to amdgpu_pm_info which reads the > > current MCLK value from the SMU. > > However, some users reported a huge perf regression >=20 > Were those private reports? If not, please consider linking them in the > trailers using Link: or Closes: tags, as explained in the patch > submission guidelines (and mandated by Linus, see the quotes and links > in > https://www.kernel.org/doc/html/latest/process/handling-regressions.html#= on-> the-importance-of-pointing-to-bug-reports-using-link-closes-tags for > details). >=20 > Ciao, Thorsten Hi Thorsten, There is no bug report. I had a conversation on Reddit which brought my=20 attention to this issue, then I actually plugged in the GPU, tested it and= =20 noticed that there is indeed a problem, and this patch here is the best fix= I=20 could find. Best regards, Timur >=20 > > and upon a closer look it seems that the GPU seems to > > not actually use the highest MCLK value, despite the SMU > > reporting that it does. > >=20 > > Let's not disable MCLK DPM on Bonaire 0x6658 (R7 260X). > >=20 > > Keep MCLK DPM disabled on R9 M380 in the 2015 iMac > > because that still hangs if we enable it. > >=20 > > Fixes: 9851f29cb06c ("drm/amd/pm/ci: Disable MCLK DPM on problematic CI > > ASICs") Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c | 7 ++----- > > 1 file changed, 2 insertions(+), 5 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c > > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c index > > 1d6e30269d56..4d553be56396 100644 > > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c > > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c > > @@ -106,11 +106,8 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) > >=20 > > hwmgr->od_enabled =3D false; > > switch (hwmgr->chip_id) { > >=20 > > case CHIP_BONAIRE: > > - /* R9 M380 in iMac 2015: SMU hangs when=20 enabling MCLK DPM > > - * R7 260X cards with old MC ucode: MCLK DPM=20 is unstable > > - */ > > - if (adev->pdev->subsystem_vendor =3D=3D 0x106B=20 || > > - adev->pdev->device =3D=3D 0x6658) { > > + /* R9 M380 in iMac 2015: SMU hangs when=20 enabling MCLK DPM */ > > + if (adev->pdev->subsystem_vendor =3D=3D 0x106B)=20 { > >=20 > > dev_info(adev->dev, "disabling=20 MCLK DPM on quirky ASIC"); > > adev->pm.pp_feature &=3D=20 ~PP_MCLK_DPM_MASK; > > hwmgr->feature_mask &=3D=20 ~PP_MCLK_DPM_MASK;