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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4854b0bff95sm46820475e9.3.2026.03.11.11.25.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Mar 2026 11:25:40 -0700 (PDT) Message-ID: Date: Wed, 11 Mar 2026 19:25:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 0/8] hw/arm/smmuv3-accel: Support AUTO properties To: Nathan Chen , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Yi Liu , Zhenzhong Duan , Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Alex Williamson , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Eric Blake , Markus Armbruster References: <20260309192119.870186-1-nathanc@nvidia.com> <33209425-ff30-4106-827f-a12a86161afb@nvidia.com> From: Eric Auger In-Reply-To: <33209425-ff30-4106-827f-a12a86161afb@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: rBRDU4hpuJ0xBRu3ZPWn0Xvw3Z3O4Uf1m1KB--kR9mY_1773253542 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 3/11/26 6:55 PM, Nathan Chen wrote: > > > On 3/11/2026 10:43 AM, Eric Auger wrote: >> >> On 3/9/26 8:21 PM, Nathan Chen wrote: >>> Hi, >>> >>> This series introduces support for specifying 'auto' for arm-smmuv3 >>> accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties. >>> When set to 'auto', these feature values are derived directly from >>> host IOMMU capabilities, avoiding the need for management layers to >>> introspect host settings. >>> >>> Accelerated SMMUv3 Address Translation Services support is derived >>> from IDR0, Range Invalidation support is derived from IDR3, Substream >>> ID size is derived from IDR1, and output address space is derived from >>> IDR5. >>> >>> Additionally, an OnOffAuto "ats" property is added for vfio-pci >>> devices, >>> where setting 'auto' detects the per-device presence of >>> IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED from the kernel, and the ATS cap can >>> be advertised or hidden by setting 'on' or 'off'. This is dependent >>> on Shameer's recent kernel series for reporting effective ATS support >>> status [0]. >>> >>> The default values are set to 'auto' for all properties. >>> >>> A complete branch can be found here: >>> https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto >> I have just noticed we are missing documentation for smmuv3 accel >> options in >> >> qemu-options.hx >> >> At the moment we just have: >> >> ``-device arm-smmuv3,primary-bus=id`` >>      This is only supported by ``-machine virt`` (ARM). >> >>      ``primary-bus=id`` >>          Accepts either the default root complex (pcie.0) or a >>          pxb-pcie based root complex. > > I will add a commit to include documentation for the smmuv3 accel > options in the next refresh.  Great. Thanks! > > Thanks, > Nathan >