Re: [PATCH i-g-t v4 4/7] tests/kms_vrr: Add new test for DC3CO validation with LOBF

["Naladala, Ramanaidu" <Ramanaidu.naladala@intel.com>]

Hi Jeevan,

On 5/11/2026 10:48 PM, Jeevan B wrote:
> Add lobf-dc3co subtest to validate DC3CO entry during link-off
> between frames.
>
> v2: Fix the flow logic.
>
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> Reviewed-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>   tests/kms_vrr.c | 34 ++++++++++++++++++++++++++++++++++
>   1 file changed, 34 insertions(+)
>
> diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
> index 6043d40f1..82eb8554a 100644
> --- a/tests/kms_vrr.c
> +++ b/tests/kms_vrr.c
> @@ -29,6 +29,7 @@
>    */
>   
>   #include "igt.h"
> +#include "igt_pm.h"
>   #include "igt_psr.h"
>   #include "i915/intel_drrs.h"
>   #include "sw_sync.h"
> @@ -76,6 +77,9 @@
>    *
>    * SUBTEST: negative-basic
>    * Description: Make sure that VRR should not be enabled on the Non-VRR panel.
> + *
> + * SUBTEST: lobf-dc3co
> + * Description: Test DC3CO entry during LOBF.
>    */
>   
>   #define NSECS_PER_SEC (1000000000ull)
> @@ -873,6 +877,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
>   	igt_assert_f(lobf_enabled, "LOBF not enabled\n");
>   }
>   
> +static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
> +			    igt_output_t *output, uint32_t flags)
> +{
> +	unsigned long dc3co_count_before, dc3co_count_after;
> +
> +	dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
> +						 IGT_INTEL_CHECK_DC3CO);
> +
> +	test_lobf(data, crtc, output, flags);
> +
> +	dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
> +						IGT_INTEL_CHECK_DC3CO);
> +
> +	igt_assert_f(dc3co_count_after > dc3co_count_before,
> +		     "DC3CO should be entered during link-off periods. "
> +		     "Before: %lu, After: %lu\n",
> +		     dc3co_count_before, dc3co_count_after);
> +}
> +
>   static void test_cleanup(data_t *data, igt_crtc_t *crtc, igt_output_t *output)
>   {
>   	igt_crtc_set_prop_value(crtc,
> @@ -1112,6 +1135,17 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
>   
>   			run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
>   		}
> +
> +		igt_describe("This test validates DC3CO entry during LOBF (Link-Off Between "
> +			     "Frames) periods while VRR is active and PSR is disabled.");
> +
> +		igt_subtest_with_dynamic("lobf-dc3co") {
> +			igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
Driver already have the display version check this check not required.
         if (DISPLAY_VER(display) >= 12) {
                 i915_reg_t dc3co_reg;

                 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
                         dc3co_reg = DG1_DMC_DEBUG3;
                         dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
                 } else {
                         dc3co_reg = TGL_DMC_DEBUG3;
                         dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
                         dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
                 }

                 seq_printf(m, "DC3CO count: %d\n",
                            intel_de_read(display, dc3co_reg));
         } else {
> +
> +			igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
> +
> +			run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF);
> +		}
>   	}
>   
>   	igt_fixture() {