From: Krzysztof Kozlowski <krzk@kernel.org>
To: E Shattow <e@freeshell.de>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Hal Feng <hal.feng@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
Date: Sat, 23 Aug 2025 17:20:03 +0200 [thread overview]
Message-ID: <fc90c450-cdb2-4bb0-bb36-5a4ccd9ba325@kernel.org> (raw)
In-Reply-To: <20250823085818.203263-2-e@freeshell.de>
On 23/08/2025 10:58, E Shattow wrote:
> Describe JH7110 SoC DDR external memory interface.
>
> Signed-off-by: E Shattow <e@freeshell.de>
Don't send the same patch multiple times. To which one people should
respond?
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-23 15:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-23 8:57 [PATCH v3 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-08-23 8:57 ` E Shattow
2025-08-23 8:58 ` [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-08-23 15:20 ` Krzysztof Kozlowski [this message]
2025-08-23 8:58 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
2025-08-23 8:58 ` E Shattow
2025-08-23 8:58 ` [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
2025-08-23 8:58 ` E Shattow
-- strict thread matches above, loose matches on Subject: below --
2025-08-23 10:01 [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-08-23 10:01 ` [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-08-23 10:01 ` E Shattow
2025-08-23 20:41 ` E Shattow
2025-08-23 20:41 ` E Shattow
2025-08-24 9:25 ` Krzysztof Kozlowski
2025-08-24 9:25 ` Krzysztof Kozlowski
2025-08-25 16:25 ` Conor Dooley
2025-08-25 16:25 ` Conor Dooley
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