Re: [PATCH v1 1/4] drm: Guard DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE behind driver feature

["Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>]

On 7/1/2026 1:39 PM, Robert Mader wrote:
> On 01.07.26 09:35, Robert Mader wrote:
>> On 30.06.26 18:57, Melissa Wen wrote:
>>>
>>>
>>> On 30/06/2026 10:42, Robert Mader wrote:
>>>> The client cap is currently advertised unconditionally, even for 
>>>> drivers that do
>>>> not support plane color pipelines. If clients supporting the later, 
>>>> like Wayland
>>>> compositors and drm_info, enable the client cap on sich drivers they 
>>>> will be
>>>> left without both color pipeline and the legacy properties 
>>>> COLOR_ENCODING and
>>>> COLOR_RANGE, effectively breaking YUV->RGB conversion support.
>>>>
>>>> Add a new driver feature and guard the client cap behind it, allowing
>>>> plane color pipeline and legacy YUV->RGB support to co-exist.
>>>
>>> Ouch, that's indeed a problem. Nice catch!
>>>
>>> I'm not sure if this is the right way to go because plane color 
>>> pipeline can be supported per plane and per hw family.
>>> My suggestion would be to only deprecate COLOR_ENCODING and 
>>> COLOR_RANGE in drm_mode_object_get_properties() if a plane 
>>> COLOR_PIPELINE property is attached.
>>> WDYT?
>>
>> Hi Melissa!
>>
>> I don't think we need or should use the legacy properties for drivers 
>> and clients that supports the new API. Once Harrys YUV conversion 
>> colorop series(1) lands, every plane on every hardware currently 
>> supporting COLOR_ENCODING and COLOR_RANGE could express that with the 
>> colorop API as well - even if not supporting any other operations.

Is it a concern then that v6.19 will have COLOR PIPELINE advertised 
without YUV support in AMD and still not allow legacy properties to be 
used? If it is, then the nuanced approach that Melissa suggested might help.

In Intel's case, currently the COLOR PIPELINE is exposed with a CTM 
block which can in theory be used for the YUV -> RGB conversion but we 
do have a dedicated programmable input CSC for this which we plan to 
expose in the near future. [1]

==
Chaitanya

[1] Note: This is in addition to the fixed matrix block that we are 
exposing for our SDR planes in

https://lore.kernel.org/intel-gfx/20260617090819.1735153-1-chaitanya.kumar.borah@intel.com/
It
>> would look roughly like this:
>>
>> └───"COLOR_PIPELINE" (atomic): enum {Bypass, YUV Pipeline 123} = Bypass
>>      ├───Bypass
>>      └───YUV Pipeline 123
>>          └───Color Operation 123
>>              └───Properties
>>                  ├───"TYPE" (immutable): enum {1D Curve, 1D LUT, 3x4 Matrix, Multiplier, 3D LUT, Fixed Matrix} = Fixed Matrix
>>                  ├───"BYPASS" (atomic): range [0, 1] = 1
>>                  ├───"NEXT" (atomic, immutable): object colorop = 465
>>                  └───"FIXED_MATRIX_TYPE" (atomic): enum {YCbCr 601 Full to RGB, YCbCr 601 Limited to RGB, YCbCr 709 Full to RGB, YCbCr 709 Limited to RGB, YCbCr 2020 NC Full to RGB, YCbCr 2020 NC Limited to RGB} = YCbCr 601 Full to RGB
>>
>> Doing so will be nicer for compositors/clients going forward as they'd 
>> only need to support a single API if they don't care about legacy 
>> drivers (and we can adapt all in-tree drivers).
>>
>> Do you agree?
>>
>> Best regards
>>
>> Robert
>>
>> 1: https://lists.freedesktop.org/archives/dri-devel/2026-June/575655.html
>>
> P.S.: sorry for the noise, just resending with all to/cc headers to make 
> sure it doesn't get lost - and wanted to add that I'm currently working 
> on the Weston implementation for the YUV conversion colorop to get it 
> over the line.
> 
> -- 
> Robert Mader
> Consultant Software Developer
> 
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