Re: [Intel-wired-lan] [PATCH v10 iwl-next 05/11] idpf: negotiate PTP capabilities and get PTP clock

[Jacob Keller <jacob.e.keller@intel.com>]

On 4/8/2025 3:30 AM, Milena Olech wrote:
> +static u64 idpf_ptp_read_src_clk_reg_direct(struct idpf_adapter *adapter,
> +					    struct ptp_system_timestamp *sts)
> +{
> +	struct idpf_ptp *ptp = adapter->ptp;
> +	u32 hi, lo;
> +
> +	spin_lock(&ptp->read_dev_clk_lock);
> +
> +	/* Read the system timestamp pre PHC read */
> +	ptp_read_system_prets(sts);
> +
> +	idpf_ptp_enable_shtime(adapter);
> +
> +	/* Read the system timestamp post PHC read */
> +	ptp_read_system_postts(sts);
> +
> +	lo = readl(ptp->dev_clk_regs.dev_clk_ns_l);
> +	hi = readl(ptp->dev_clk_regs.dev_clk_ns_h);
> +
> +	spin_unlock(&ptp->read_dev_clk_lock);
> +
> +	return ((u64)hi << 32) | lo;
> +}
v9 had comments regarding the latching of the registers for direct
access. Can you confirm whether this is known to be safe, or if you need
to implement a 3-part read like we do in ice and other hardware? Even
with a spinlock there could be issues with rollover in the hardware I think?

Thanks,
Jake