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From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Mon, 24 Aug 2026 10:20:26 -0500 In-Reply-To: <20260820140114.327023-24-rathc@linux.ibm.com> References: <20260820140114.327023-1-rathc@linux.ibm.com> <20260820140114.327023-24-rathc@linux.ibm.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDEyNiBTYWx0ZWRfX4Uu4qx4VrTvX qrQRtpPo0AE3G4hekYgkzaVSrUIimlOU2gfMi2N69DRrbi2ufC1CXj4qv4QScKHXgNjP2Oq27V2 oeXO6YYKqhEIBCdC1vSyH5ewfKWK0Tc= X-Authority-Analysis: v=2.4 cv=AYuB2XXG c=1 sm=1 tr=0 ts=6a8c6140 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=paC7c6kxKwQgFw3nImoA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: krL2EVGLOj32a6ibVkbQL5Hg6XUGL-M7 X-Proofpoint-GUID: ZhCa87xGE7yPlqYnFW_kVuZyhxMEbhAY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDEyNiBTYWx0ZWRfX8yoZl7QhGidz xRAgOM9e5DAgH7TJvYqzb7zGg7hsYMszSNsjiggLH/7dJumAtENjDI26J/Eopr9nJgY1fi0G0Qp dL7Sq93XcJ6PoBCp9xbfCEkfMVHUWB/9I+4e4w0Y2ST3ONiz0uJXxFjPDrkL0+a+h+s8AJhFnM4 Ouw6ECK4U0EP92sk68yMZCBTM/7oRZJijC0OTO7orkVxXCSTvXsglS82KsmKdWIVQdS9YKj4jXd jooys1rd768RxP6Sxa9UWSg+V6I9+OkXr0Ji8W17FmBV5wpJfTnkKOiLqOfWXqRwI2FEgARMX95 cuDk1oWZ9OPBDC6YVJ2oBUUOVPEIQwwoIwaGMoGAwqqThi6suyHgNg0wXBhXpLoghwlByh20NrL 5hYugDNMjy4jvgPT5YCkNKOTneH9+/Y5KlFmx7EGJnCFxAgH3guHlgHxl4wDvsCiRWjqMyWHLdg 8fXkWiLtBduuBh0s47g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_04,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240126 Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Thu, 2026-08-20 at 19:30 +0530, Chinmay Rath wrote: > From: Shivang Upadhyay > > Move below instructions to decodetree specification : > > lsw{i, x}, > stsw{i, x} : X-form > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag. > > Signed-off-by: Shivang Upadhyay > Signed-off-by: Chinmay Rath > --- > target/ppc/helper.h | 6 +- > target/ppc/insn32.decode | 7 ++ > target/ppc/mem_helper.c | 6 +- > target/ppc/translate.c | 102 -------------------- > target/ppc/translate/fixedpoint-impl.c.inc | 103 +++++++++++++++++++++ > 5 files changed, 116 insertions(+), 108 deletions(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 7e15676122..0e8b96d0ec 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -45,9 +45,9 @@ DEF_HELPER_1(check_tlb_flush_global, void, env) > > DEF_HELPER_3(lmw, void, env, tl, i32) > DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) > -DEF_HELPER_4(lsw, void, env, tl, i32, i32) > -DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) > -DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32) > +DEF_HELPER_4(LSW, void, env, tl, i32, i32) > +DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) > +DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) > DEF_HELPER_FLAGS_3(DCBZ, TCG_CALL_NO_WG, void, env, tl, int) > #ifdef TARGET_PPC64 > DEF_HELPER_FLAGS_2(DCBZL, TCG_CALL_NO_WG, void, env, tl) > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index a3973e042d..e7b5d19cde 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -527,6 +527,13 @@ CREQV 010011 ..... ..... ..... 0100100001 - @X > CRANDC 010011 ..... ..... ..... 0010000001 - @X > CRORC 010011 ..... ..... ..... 0110100001 - @X > > +# Fixed Point Move Assist Instructions > + > +LSWI 011111 ..... ..... ..... 1 001010101 - @X > +LSWX 011111 ..... ..... ..... 1 000010101 - @X > +STSWI 011111 ..... ..... ..... 1 011010101 - @X > +STSWX 011111 ..... ..... ..... 1 010010101 - @X > + > # Fixed-Point Hash Instructions > > HASHST 011111 ..... ..... ..... 1011010010 . @X_DW > diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c > index 95a224e74c..582180cf88 100644 > --- a/target/ppc/mem_helper.c > +++ b/target/ppc/mem_helper.c > @@ -190,7 +190,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, > env->gpr[reg] = val; > } > > -void helper_lsw(CPUPPCState *env, target_ulong addr, > +void helper_LSW(CPUPPCState *env, target_ulong addr, > uint32_t nb, uint32_t reg) > { > do_lsw(env, addr, nb, reg, GETPC()); > @@ -202,7 +202,7 @@ void helper_lsw(CPUPPCState *env, target_ulong addr, > * this is valid, but rA won't be loaded. For now, I'll follow the > * spec... > */ > -void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, > +void helper_LSWX(CPUPPCState *env, target_ulong addr, uint32_t reg, > uint32_t ra, uint32_t rb) > { > if (likely(xer_bc != 0)) { > @@ -218,7 +218,7 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, > } > } > > -void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, > +void helper_STSW(CPUPPCState *env, target_ulong addr, uint32_t nb, > uint32_t reg) > { > uintptr_t raddr = GETPC(); > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index e40841b68e..712990cf2d 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2595,104 +2595,6 @@ static void gen_stmw(DisasContext *ctx) > gen_helper_stmw(tcg_env, t0, t1); > } > > -/*** Integer load and store strings ***/ > - > -/* lswi */ > -/* > - * PowerPC32 specification says we must generate an exception if rA is > - * in the range of registers to be loaded. In an other hand, IBM says > - * this is valid, but rA won't be loaded. For now, I'll follow the > - * spec... > - */ > -static void gen_lswi(DisasContext *ctx) > -{ > - TCGv t0; > - TCGv_i32 t1, t2; > - int nb = NB(ctx->opcode); > - int start = rD(ctx->opcode); > - int ra = rA(ctx->opcode); > - int nr; > - > - if (ctx->le_mode) { > - gen_align_no_le(ctx); > - return; > - } > - if (nb == 0) { > - nb = 32; > - } > - nr = DIV_ROUND_UP(nb, 4); > - if (unlikely(lsw_reg_in_range(start, nr, ra))) { > - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); > - return; > - } > - gen_set_access_type(ctx, ACCESS_INT); > - t0 = tcg_temp_new(); > - gen_addr_register(ctx, t0); > - t1 = tcg_constant_i32(nb); > - t2 = tcg_constant_i32(start); > - gen_helper_lsw(tcg_env, t0, t1, t2); > -} > - > -/* lswx */ > -static void gen_lswx(DisasContext *ctx) > -{ > - TCGv t0; > - TCGv_i32 t1, t2, t3; > - > - if (ctx->le_mode) { > - gen_align_no_le(ctx); > - return; > - } > - gen_set_access_type(ctx, ACCESS_INT); > - t0 = tcg_temp_new(); > - gen_addr_reg_index(ctx, t0); > - t1 = tcg_constant_i32(rD(ctx->opcode)); > - t2 = tcg_constant_i32(rA(ctx->opcode)); > - t3 = tcg_constant_i32(rB(ctx->opcode)); > - gen_helper_lswx(tcg_env, t0, t1, t2, t3); > -} > - > -/* stswi */ > -static void gen_stswi(DisasContext *ctx) > -{ > - TCGv t0; > - TCGv_i32 t1, t2; > - int nb = NB(ctx->opcode); > - > - if (ctx->le_mode) { > - gen_align_no_le(ctx); > - return; > - } > - gen_set_access_type(ctx, ACCESS_INT); > - t0 = tcg_temp_new(); > - gen_addr_register(ctx, t0); > - if (nb == 0) { > - nb = 32; > - } > - t1 = tcg_constant_i32(nb); > - t2 = tcg_constant_i32(rS(ctx->opcode)); > - gen_helper_stsw(tcg_env, t0, t1, t2); > -} > - > -/* stswx */ > -static void gen_stswx(DisasContext *ctx) > -{ > - TCGv t0; > - TCGv_i32 t1, t2; > - > - if (ctx->le_mode) { > - gen_align_no_le(ctx); > - return; > - } > - gen_set_access_type(ctx, ACCESS_INT); > - t0 = tcg_temp_new(); > - gen_addr_reg_index(ctx, t0); > - t1 = tcg_temp_new_i32(); > - tcg_gen_trunc_tl_i32(t1, cpu_xer); > - tcg_gen_andi_i32(t1, t1, 0x7F); > - t2 = tcg_constant_i32(rS(ctx->opcode)); > - gen_helper_stsw(tcg_env, t0, t1, t2); > -} > > #if !defined(CONFIG_USER_ONLY) > static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) > @@ -4914,10 +4816,6 @@ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), > GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), > GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > -GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), > -GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), > -GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), > -GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), > /* ISA v3.0 changed the extended opcode from 62 to 30 */ > GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), > #if defined(TARGET_PPC64) > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index 26b308e435..82fb645279 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -585,6 +585,109 @@ TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); > TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); > TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); > > + > +/*** Integer load and store strings ***/ > + > +/* lswi */ > +static bool trans_LSWI(DisasContext *ctx, arg_LSWI *a) > +{ > + TCGv t0; > + TCGv_i32 t1, t2; > + int nb = a->rb; > + int start = a->rt; > + int ra = a->ra; > + int nr; > + > + REQUIRE_INSNS_FLAGS(ctx, STRING); > + if (ctx->le_mode) { > + gen_align_no_le(ctx); > + return true; > + } > + if (nb == 0) { > + nb = 32; > + } > + nr = DIV_ROUND_UP(nb, 4); > + if (unlikely(lsw_reg_in_range(start, nr, ra))) { > + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); > + return true; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + t0 = do_ea_calc_ra(ctx, ra); > + t1 = tcg_constant_i32(nb); > + t2 = tcg_constant_i32(start); > + gen_helper_LSW(tcg_env, t0, t1, t2); > + > + return true; > +} > + > +/* lswx */ > +static bool trans_LSWX(DisasContext *ctx, arg_LSWX *a) > +{ > + TCGv t0; > + TCGv_i32 t1, t2, t3; > + > + REQUIRE_INSNS_FLAGS(ctx, STRING); > + if (ctx->le_mode) { > + gen_align_no_le(ctx); > + return true; > + } > + > + gen_set_access_type(ctx, ACCESS_INT); > + t0 = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); > + t1 = tcg_constant_i32(a->rt); > + t2 = tcg_constant_i32(a->ra); > + t3 = tcg_constant_i32(a->rb); > + gen_helper_LSWX(tcg_env, t0, t1, t2, t3); > + > + return true; > +} > + > +/* stswi */ > +static bool trans_STSWI(DisasContext *ctx, arg_STSWI *a) > +{ > + TCGv t0; > + TCGv_i32 t1, t2; > + int nb = a->rb; > + > + REQUIRE_INSNS_FLAGS(ctx, STRING); > + if (ctx->le_mode) { > + gen_align_no_le(ctx); > + return true; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + t0 = do_ea_calc_ra(ctx, a->ra); > + if (nb == 0) { > + nb = 32; > + } > + t1 = tcg_constant_i32(nb); > + t2 = tcg_constant_i32(a->rt); > + gen_helper_STSW(tcg_env, t0, t1, t2); > + > + return true; > +} > + > +/* stswx */ > +static bool trans_STSWX(DisasContext *ctx, arg_STSWX *a) > +{ > + TCGv t0; > + TCGv_i32 t1, t2; > + > + REQUIRE_INSNS_FLAGS(ctx, STRING); > + if (ctx->le_mode) { > + gen_align_no_le(ctx); > + return true; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + t0 = do_ea_calc_ra(ctx, a->ra); > + t1 = tcg_temp_new_i32(); > + tcg_gen_trunc_tl_i32(t1, cpu_xer); > + tcg_gen_andi_i32(t1, t1, 0x7F); > + t2 = tcg_constant_i32(a->rt); > + gen_helper_STSW(tcg_env, t0, t1, t2); > + > + return true; > +} > + > static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca, > bool compute_ov, bool compute_rc0) > {