Re: [PATCH net v3 08/14] ice: E825: stop clearing PHY_REG_TX_OFFSET_READY

[Jacob Keller <jacob.e.keller@intel.com>]

On 10/19/2026 4:42 PM, Jacob Keller wrote:
> On 10/19/2026 1:14 PM, netdev-bot+sashiko@kernel.org wrote:
>> Suppose the first register write in ice_start_phy_timer_eth56g() fails:
>>
>> ice_start_phy_timer_eth56g()
>>     err = ice_stop_phy_timer_eth56g(hw, port);
>>     if (err)
>>         return err;
>>
>> PHY_REG_RX_OFFSET_READY then keeps its previous value, for example 1 from
>> an earlier successful start. The hardware may keep marking Rx descriptor
>> timestamps valid, even though ice_sync_phy_timer_eth56g() never ran.
>>
>> If any later step fails, RX_OFFSET_READY has already been cleared and the
>> message is accurate. The early return is not new; only the message's
>> absolute claim is.
>>
>> Could the message be more precise here, for example by saying that Tx
>> timestamping remains disabled?
>>
> 
> I can fix this.
> 

On a second re-read, I think this is overly pedantic. Strictly speaking
Rx offset might be valid but in practice the entire reset sequence
didn't occur and it is likely that timestamps are still broken. I think
leaving this as is is good enough for end users and system
administrators who need to be made aware that a link restart is
potentially required to fix the unexpected failure.