Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables

[Dinh Nguyen <dinguyen@kernel.org>]

On 4/22/25 07:22, Thorsten Blum wrote:
> On 8. Apr 2025, at 19:45, Thorsten Blum wrote:
>> On 19. Feb 2025, at 13:42, Dinh Nguyen wrote:
>>> On 2/19/25 04:42, Thorsten Blum wrote:
>>>> Since readl() returns a u32, the local variables reg and bypass can also
>>>> have the data type u32. Furthermore, divf and divq are derived from reg
>>>> and can also be a u32.
>>>> Since do_div() casts the divisor to u32 anyway, changing the data type
>>>> of divq to u32 removes the following Coccinelle/coccicheck warning
>>>> reported by do_div.cocci:
>>>> WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>>>> Compile-tested only.
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
>>>> ---
>>>> drivers/clk/socfpga/clk-pll.c | 4 ++--
>>>
>>> Applied!
>>
>> Did this patch and [*] get lost somehow?
>>
>> They aren't in -next and also didn't make it into the last merge window.
> 
> Does anybody else know what happened or where I could find them?
> 

This is my bad. I missed the merge window for the PR. I'll resend it 
this time.

Dinh