From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [Patch v4 09/13] perf/x86/intel: Setup PEBS data configuration and enable legacy groups
Date: Mon, 23 Jun 2025 09:55:48 +0800 [thread overview]
Message-ID: <fe19ce39-689c-419b-9073-7fcaacd2841f@linux.intel.com> (raw)
In-Reply-To: <20250621094343.GY1613376@noisy.programming.kicks-ass.net>
On 6/21/2025 5:43 PM, Peter Zijlstra wrote:
> On Fri, Jun 20, 2025 at 10:39:05AM +0000, Dapeng Mi wrote:
>
>> + if (cpuc->n_pebs == cpuc->n_large_pebs)
>> + index.split.thresh = ARCH_PEBS_THRESH_MUL;
>> + else
>> + index.split.thresh = ARCH_PEBS_THRESH_SINGLE;
>> + if (cpuc->n_pebs == cpuc->n_large_pebs)
>> + index.split.thresh = ARCH_PEBS_THRESH_MUL;
>> + else
>> + index.split.thresh = ARCH_PEBS_THRESH_SINGLE;
>> +/*
>> + * The largest PEBS record could consume a page, ensure
>> + * a record at least can be written after triggering PMI.
>> + */
>> +#define ARCH_PEBS_THRESH_MUL ((PEBS_BUFFER_SIZE - PAGE_SIZE) >> PEBS_BUFFER_SHIFT)
>> +#define ARCH_PEBS_THRESH_SINGLE 1
> Can we please do something like s/MUL/MULTI/ or so. My brain keeps
> trying to make it MULtiply and that doesn't really work.
Sure.
next prev parent reply other threads:[~2025-06-23 1:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 10:38 [Patch v4 00/13] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-06-20 10:38 ` [Patch v4 01/13] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-06-20 10:38 ` [Patch v4 02/13] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
2025-06-20 10:38 ` [Patch v4 03/13] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 04/13] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-06-20 10:39 ` [Patch v4 05/13] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-06-20 10:39 ` [Patch v4 06/13] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-06-20 10:39 ` [Patch v4 07/13] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-06-21 9:20 ` Peter Zijlstra
2025-06-23 1:17 ` Mi, Dapeng
2025-06-23 7:28 ` Peter Zijlstra
2025-06-23 8:41 ` Mi, Dapeng
2025-06-20 10:39 ` [Patch v4 08/13] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-06-20 10:39 ` [Patch v4 09/13] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-06-21 9:27 ` Peter Zijlstra
2025-06-23 1:20 ` Mi, Dapeng
2025-06-21 9:34 ` Peter Zijlstra
2025-06-23 1:38 ` Mi, Dapeng
2025-06-21 9:36 ` Peter Zijlstra
2025-06-23 1:39 ` Mi, Dapeng
2025-06-21 9:41 ` Peter Zijlstra
2025-06-23 1:55 ` Mi, Dapeng
2025-06-21 9:43 ` Peter Zijlstra
2025-06-23 1:55 ` Mi, Dapeng [this message]
2025-06-20 10:39 ` [Patch v4 10/13] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 11/13] perf/x86: Support to sample SSP register Dapeng Mi
2025-06-20 10:39 ` [Patch v4 12/13] perf/x86/intel: Support to sample SSP register for arch-PEBS Dapeng Mi
2025-06-20 10:39 ` [Patch v4 13/13] perf tools: x86: Support to show SSP register Dapeng Mi
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