diff for duplicates of <fe1d445e-e9ac-452f-e990-d4bc17bd3355@phytec.de> diff --git a/a/1.txt b/N1/1.txt index fb5b4d7..3a31294 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,9 +1,9 @@ Hi, -On 03/05/2018 10:08 PM, Heiko Stübner wrote: -> Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner: ->> Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: +On 03/05/2018 10:08 PM, Heiko St?bner wrote: +> Am Montag, 5. M?rz 2018, 21:25:30 CET schrieb Heiko St?bner: +>> Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz: >>> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. >>> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. >>> @@ -25,6 +25,6 @@ It's not so urgent because the RK818 PMIC currently does not boot and the patch for this problem is also pending. -- -Mit freundlichen Grüßen, +Mit freundlichen Gr??en, With best regards, Daniel Schultz diff --git a/a/content_digest b/N1/content_digest index b1f7a48..bda82a9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,26 +1,18 @@ "ref\01520253911-46218-1-git-send-email-d.schultz@phytec.de\0" "ref\03380975.Amu1WGHSQ5@diego\0" "ref\02707703.8mZIocJ1Ne@diego\0" - "From\0Daniel Schultz <d.schultz@phytec.de>\0" - "Subject\0Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing\0" + "From\0d.schultz@phytec.de (Daniel Schultz)\0" + "Subject\0[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing\0" "Date\0Tue, 6 Mar 2018 10:59:54 +0100\0" - "To\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Cc\0robh+dt@kernel.org" - mark.rutland@arm.com - linux@armlinux.org.uk - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - " w.egorov@phytec.de\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi,\n" "\n" "\n" - "On 03/05/2018 10:08 PM, Heiko St\303\274bner wrote:\n" - "> Am Montag, 5. M\303\244rz 2018, 21:25:30 CET schrieb Heiko St\303\274bner:\n" - ">> Am Montag, 5. M\303\244rz 2018, 13:45:11 CET schrieb Daniel Schultz:\n" + "On 03/05/2018 10:08 PM, Heiko St?bner wrote:\n" + "> Am Montag, 5. M?rz 2018, 21:25:30 CET schrieb Heiko St?bner:\n" + ">> Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:\n" ">>> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.\n" ">>> Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.\n" ">>>\n" @@ -42,8 +34,8 @@ "the patch for this problem is also pending.\n" "\n" "-- \n" - "Mit freundlichen Gr\303\274\303\237en,\n" + "Mit freundlichen Gr??en,\n" "With best regards,\n" Daniel Schultz -d32d238dbe9acd0682001385ba540e345ed2529fda1e8d8231818e2eb00746f0 +4013dedafe7145d7ffec6a09df30a84f45d409059e1c64dde0695d406e7465e5
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