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[189.69.160.78]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c355aeaae3sm4370170a12.43.2024.06.02.16.00.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Jun 2024 16:00:50 -0700 (PDT) Message-ID: Date: Sun, 2 Jun 2024 20:00:45 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 To: Alexey Baturo Cc: richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20240511101053.1875596-1-me@deliversmonkey.space> <20240511101053.1875596-3-me@deliversmonkey.space> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20240511101053.1875596-3-me@deliversmonkey.space> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/11/24 7:10 AM, Alexey Baturo wrote: > From: Alexey Baturo > > Signed-off-by: Alexey Baturo > > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.h | 8 ++++++++ > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_cfg.h | 3 +++ > target/riscv/csr.c | 11 +++++++++++ > target/riscv/machine.c | 10 +++++++--- > target/riscv/pmp.c | 13 ++++++++++--- > target/riscv/pmp.h | 11 ++++++----- > 7 files changed, 48 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 232521bb87..52b6ba73c8 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -121,6 +121,14 @@ typedef enum { > EXT_STATUS_DIRTY, > } RISCVExtStatus; > > +/* Enum holds PMM field values for Zjpm v0.8 extension */ > +typedef enum { > + PMM_FIELD_DISABLED = 0, > + PMM_FIELD_RESERVED = 1, > + PMM_FIELD_PMLEN7 = 2, > + PMM_FIELD_PMLEN16 = 3, > +} RISCVPmPmm; > + > #define MMU_USER_IDX 3 > > #define MAX_RISCV_PMPS (16) > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index da16ba236a..13ce2218d1 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -708,6 +708,7 @@ typedef enum RISCVException { > #define MENVCFG_CBIE (3UL << 4) > #define MENVCFG_CBCFE BIT(6) > #define MENVCFG_CBZE BIT(7) > +#define MENVCFG_PMM (3ULL << 32) > #define MENVCFG_ADUE (1ULL << 61) > #define MENVCFG_PBMTE (1ULL << 62) > #define MENVCFG_STCE (1ULL << 63) > @@ -721,11 +722,13 @@ typedef enum RISCVException { > #define SENVCFG_CBIE MENVCFG_CBIE > #define SENVCFG_CBCFE MENVCFG_CBCFE > #define SENVCFG_CBZE MENVCFG_CBZE > +#define SENVCFG_PMM MENVCFG_PMM > > #define HENVCFG_FIOM MENVCFG_FIOM > #define HENVCFG_CBIE MENVCFG_CBIE > #define HENVCFG_CBCFE MENVCFG_CBCFE > #define HENVCFG_CBZE MENVCFG_CBZE > +#define HENVCFG_PMM MENVCFG_PMM > #define HENVCFG_ADUE MENVCFG_ADUE > #define HENVCFG_PBMTE MENVCFG_PBMTE > #define HENVCFG_STCE MENVCFG_STCE > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index e1e4f32698..9ecdc792c5 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -120,6 +120,9 @@ struct RISCVCPUConfig { > bool ext_ssaia; > bool ext_sscofpmf; > bool ext_smepmp; > + bool ext_ssnpm; > + bool ext_smnpm; > + bool ext_smmpm; > bool rvv_ta_all_1s; > bool rvv_ma_all_1s; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 4b2c932564..45b548eb0b 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -530,6 +530,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno) > if (riscv_cpu_cfg(env)->ext_zkr) { > return RISCV_EXCP_NONE; > } > + if (riscv_cpu_cfg(env)->ext_smmpm) { > + return RISCV_EXCP_NONE; > + } > > return RISCV_EXCP_ILLEGAL_INST; > } > @@ -2083,6 +2086,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > (cfg->ext_svadu ? MENVCFG_ADUE : 0); > } > + /* Update PMM field only if the value is valid according to Zjpm v0.8 */ > + if (((val & MENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) { > + mask |= MENVCFG_PMM; > + } > env->menvcfg = (env->menvcfg & ~mask) | (val & mask); > > return RISCV_EXCP_NONE; > @@ -2127,6 +2134,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > target_ulong val) > { > uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; > + /* Update PMM field only if the value is valid according to Zjpm v0.8 */ > + if (((val & SENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) { > + mask |= SENVCFG_PMM; > + } > RISCVException ret; > > ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 64ab66e332..bbbb28f373 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -152,15 +152,19 @@ static const VMStateDescription vmstate_vector = { > > static bool pointermasking_needed(void *opaque) > { > - return false; > + RISCVCPU *cpu = opaque; > + return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm; > } > > static const VMStateDescription vmstate_pointermasking = { > .name = "cpu/pointer_masking", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .needed = pointermasking_needed, > .fields = (const VMStateField[]) { > + VMSTATE_UINTTL(env.mseccfg, RISCVCPU), > + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), > VMSTATE_END_OF_LIST() > } These fields are already being added in the machine vmstate via vmstate_envcfg, added via commit 29a9ec9b, "target/riscv: Add *envcfg* CSRs support": static const VMStateDescription vmstate_envcfg = { .name = "cpu/envcfg", .version_id = 1, .minimum_version_id = 1, .needed = envcfg_needed, .fields = (const VMStateField[]) { VMSTATE_UINT64(env.menvcfg, RISCVCPU), VMSTATE_UINTTL(env.senvcfg, RISCVCPU), VMSTATE_UINT64(env.henvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } }; You need to keep both pointermasking_needed() and vmstate_pointermasking untouched. Doing that will also fix the build problem that Alistair mentioned in his reply. Thanks, Daniel > }; > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 2a76b611a0..7ddb9dbf0b 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -574,6 +574,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) > void mseccfg_csr_write(CPURISCVState *env, target_ulong val) > { > int i; > + uint64_t mask = MSECCFG_MMWP | MSECCFG_MML; > + > + /* Update PMM field only if the value is valid according to Zjpm v0.8 */ > + if (((val & MSECCFG_PMM) >> 32) != PMM_FIELD_RESERVED) { > + mask |= MSECCFG_PMM; > + } > > trace_mseccfg_csr_write(env->mhartid, val); > > @@ -589,12 +595,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) > > if (riscv_cpu_cfg(env)->ext_smepmp) { > /* Sticky bits */ > - val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); > - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { > + val |= (env->mseccfg & mask); > + if ((val ^ env->mseccfg) & mask) { > tlb_flush(env_cpu(env)); > } > } else { > - val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); > + mask |= MSECCFG_RLB; > + val &= ~(mask); > } > > env->mseccfg = val; > diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h > index f5c10ce85c..ccff0eb9b6 100644 > --- a/target/riscv/pmp.h > +++ b/target/riscv/pmp.h > @@ -40,11 +40,12 @@ typedef enum { > } pmp_am_t; > > typedef enum { > - MSECCFG_MML = 1 << 0, > - MSECCFG_MMWP = 1 << 1, > - MSECCFG_RLB = 1 << 2, > - MSECCFG_USEED = 1 << 8, > - MSECCFG_SSEED = 1 << 9 > + MSECCFG_MML = 1 << 0, > + MSECCFG_MMWP = 1 << 1, > + MSECCFG_RLB = 1 << 2, > + MSECCFG_USEED = 1 << 8, > + MSECCFG_SSEED = 1 << 9, > + MSECCFG_PMM = 3UL << 32, > } mseccfg_field_t; > > typedef struct {