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([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-52c53865814sm11023821e0c.38.2025.05.15.04.11.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 04:11:38 -0700 (PDT) Message-ID: Date: Thu, 15 May 2025 08:11:34 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] target/riscv: Add the implied rule for G extension To: frank.chang@sifive.com, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , "open list:RISC-V TCG CPUs" , Jim Shu References: <20250514041118.1614-1-frank.chang@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250514041118.1614-1-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::a31; envelope-from=dbarboza@ventanamicro.com; helo=mail-vk1-xa31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/14/25 1:11 AM, frank.chang@sifive.com wrote: > From: Jim Shu > > Add the missing implied rule from G to imafd_zicsr_zifencei. > > Signed-off-by: Jim Shu > Reviewed-by: Frank Chang > --- Patch LGTM. I believe this will deprecate everything we're doing in riscv_cpu_validate_g() in tcg-cpu.c and we should remove it in this same patch. Thanks, Daniel > target/riscv/cpu.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d92874baa0..27edd5af62 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2520,6 +2520,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule RVG_IMPLIED = { > + .is_misa = true, > + .ext = RVG, > + .implied_misa_exts = RVI | RVM | RVA | RVF | RVD, > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_zicsr), > + CPU_CFG_OFFSET(ext_zifencei), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > static RISCVCPUImpliedExtsRule ZCB_IMPLIED = { > .ext = CPU_CFG_OFFSET(ext_zcb), > .implied_multi_exts = { > @@ -2898,7 +2910,7 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = { > > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > - &RVM_IMPLIED, &RVV_IMPLIED, NULL > + &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL > }; > > RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {