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[83.11.22.169]) by smtp.gmail.com with ESMTPSA id g3-20020a056402180300b00566ea8e9f38sm7001471edy.40.2024.03.07.14.15.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Mar 2024 14:15:43 -0800 (PST) Message-ID: Date: Thu, 7 Mar 2024 23:15:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 0/2] Add RISC-V Server Platform Reference Board Content-Language: pl-PL, en-GB, en-HK To: Fei Wu , pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, andrei.warkentin@intel.com, shaolin.xie@alibaba-inc.com, ved@rivosinc.com, sunilvl@ventanamicro.com, haibo1.xu@intel.com, evan.chai@intel.com, yin.wang@intel.com, tech-server-platform@lists.riscv.org, tech-server-soc@lists.riscv.org References: <20240304102540.2789225-1-fei2.wu@intel.com> From: Marcin Juszkiewicz Organization: Linaro In-Reply-To: <20240304102540.2789225-1-fei2.wu@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org W dniu 4.03.2024 o 11:25, Fei Wu pisze: > The RISC-V Server Platform specification[1] defines a standardized > set of hardware and software capabilities, that portable system > software, such as OS and hypervisors can rely on being present in a > RISC-V server platform. This patchset provides a RISC-V Server > Platform (RVSP) reference implementation on qemu which is in > compliance with the spec as faithful as possible. I am working on sbsa-ref which is AArch64 Standard Server Platform implementation. Will not go through details of rvsp-ref but give some potential hints from my work with our platform. 1. Consider versioning the platform. We have 'platform_version'.'major/minor' exported in DeviceTree-formatted data. This allows for firmware to know which of non-discoverable hardware features exists and which not. We use it to disable XHCI controller on older platform version. 2. If specification allows to have non-discoverable devices then add some. This will require you to handle them in firmware in some way. Sooner or later some physical hardware will be in same situation so they can use your firmware code as reference. We have AHCI and XHCI on system bus (hardcoded in firmware). 3. You are going to use EDK2 with ACPI. Hide DT from code there with some hardware information library. For sbsa-ref we created SbsaHardwareInfoLib in https://openfw.io/edk2-devel/20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org/ patchset.