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To: Richard Henderson , Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, npiggin@gmail.com, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240607144921.726730-1-rathc@linux.ibm.com> <20240607144921.726730-4-rathc@linux.ibm.com> <28ea359e-fdbf-4a4f-b004-19e558d8d96f@linaro.org> Content-Language: en-US From: Chinmay Rath In-Reply-To: <28ea359e-fdbf-4a4f-b004-19e558d8d96f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 4_IxO5F73nNmtJr5joKgLpD1xapj8zuM X-Proofpoint-GUID: ii1QwQC4qO2mRm1Q-C39JCKXYq_u4gOi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-09_14,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=911 clxscore=1015 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406090145 Received-SPF: none client-ip=148.163.158.5; envelope-from=rathc@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 6/7/24 21:16, Richard Henderson wrote: > On 6/7/24 07:49, Chinmay Rath wrote: >> Moving the following instructions to decodetree specification: >> >>    lxv{b16, d2, h8, w4, ds, ws}x   : X-form >>    stxv{b16, d2, h8, w4}x          : X-form >> >> The changes were verified by validating that the tcg-ops generated >> for those >> instructions remain the same, which were captured using the '-d >> in_asm,op' flag. >> >> Signed-off-by: Chinmay Rath >> --- >>   target/ppc/insn32.decode            |  10 ++ >>   target/ppc/translate/vsx-impl.c.inc | 199 ++++++++++++---------------- >>   target/ppc/translate/vsx-ops.c.inc  |  12 -- >>   3 files changed, 97 insertions(+), 124 deletions(-) > > Because the ops are identical, > Reviewed-by: Richard Henderson > > But you really should update these to use tcg_gen_qemu_ld/st_i128 with > the proper atomicity flags.  This will fix an existing bug... > ^ Surely Richard, I have noted this suggestion of yours from an earlier patch, and plan to do this change and implement a few of your other suggestions,     which I couldn't implement earlier, along with some clean-ups this week.     I refrained from doing it with the decodetree movement, to take proper time to understand and test.     Should send out those patches soon.     Thanks & Regards,     Chinmay >> +static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a) >>   { >>       TCGv EA; >>       TCGv_i64 t0; >> + >> +    REQUIRE_VSX(ctx); >> +    REQUIRE_INSNS_FLAGS2(ctx, VSX); >> + >>       t0 = tcg_temp_new_i64(); >>       gen_set_access_type(ctx, ACCESS_INT); >> +    EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); >>       gen_qemu_ld64_i64(ctx, t0, EA); >> +    set_cpu_vsr(a->rt, t0, true); > > where the vector register is partially modified ... > >>       tcg_gen_addi_tl(EA, EA, 8); >>       gen_qemu_ld64_i64(ctx, t0, EA); > > before a fault from the second load is recognized. > Similarly for stores leaving memory partially modified. > > > r~ > >