From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v1 2/2] drm/xe: Add sysfs for GT/IA bias
Date: Sun, 5 Jul 2026 01:04:44 -0700 [thread overview]
Message-ID: <ffbde075-78cf-4337-af89-e73f6b159802@intel.com> (raw)
In-Reply-To: <akgAD4rCNg1Ztdxb@intel.com>
On 7/3/2026 11:31 AM, Rodrigo Vivi wrote:
> On Wed, Jul 01, 2026 at 05:56:14PM -0700, Vinay Belgaumkar wrote:
>> GT_IA_PERF_BIAS_REG indicates power budget between IA and GT.
>> Lower 16 bits correspond to IA and upper to GT. Higher value
>> indicates more bias towards that plane. The values are in U1.15
>> format.
>>
>> $ cat /sys/class/drm/card1/device/tile0/gt0/freq0/gt_ia_bias
>> 0x80002666
> What about decoding this?
With the standard U1.15 format, this represents fractions with max value
of 1. So, 0x8000 is decoded as 0x8000/2^15, which is 1. Every other
number will be less than 1. I could add the decoding if that adds value.
Thanks,
Vinay.
>
>> This interface will allow us to observe power budget changes while
>> running workloads and also, if needed, tune it.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
>> drivers/gpu/drm/xe/xe_gt_freq.c | 51 ++++++++++++++++++++++++++++
>> 2 files changed, 53 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 08251c7a1a4b..41c5c5f20964 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -634,6 +634,8 @@
>> #define GT_GFX_RC6_LOCKED XE_REG(0x138104)
>> #define GT_GFX_RC6 XE_REG(0x138108)
>>
>> +#define GT_IA_PERF_BIAS_REG XE_REG(0x138158)
>> +
>> #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8)
>> /* Common performance limit reason bits - available on all platforms */
>> #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
>> diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c
>> index a40dd074106f..0847832151f9 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_freq.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_freq.c
>> @@ -11,10 +11,13 @@
>> #include <drm/drm_managed.h>
>> #include <drm/drm_print.h>
>>
>> +#include <regs/xe_gt_regs.h>
>> +#include "xe_gt.h"
>> #include "xe_gt_sysfs.h"
>> #include "xe_gt_throttle.h"
>> #include "xe_gt_types.h"
>> #include "xe_guc_pc.h"
>> +#include "xe_mmio.h"
>> #include "xe_pm.h"
>>
>> /**
>> @@ -242,6 +245,41 @@ static ssize_t power_profile_store(struct kobject *kobj,
>> }
>> static struct kobj_attribute attr_power_profile = __ATTR_RW(power_profile);
>>
>> +static ssize_t gt_ia_bias_show(struct kobject *kobj,
>> + struct kobj_attribute *attr,
>> + char *buf)
>> +{
>> + struct device *dev = kobj_to_dev(kobj);
>> + struct xe_gt *gt = kobj_to_gt(kobj->parent);
>> + u32 val;
>> +
>> + guard(xe_pm_runtime)(dev_to_xe(dev));
>> + val = xe_mmio_read32(>->mmio, GT_IA_PERF_BIAS_REG);
>> +
>> + return sysfs_emit(buf, "0x%x\n", val);
>> +}
>> +
>> +static ssize_t gt_ia_bias_store(struct kobject *kobj,
>> + struct kobj_attribute *attr,
>> + const char *buff, size_t count)
>> +{
>> + struct device *dev = kobj_to_dev(kobj);
>> + struct xe_gt *gt = kobj_to_gt(kobj->parent);
>> + u32 val;
>> + int ret;
>> +
>> + ret = kstrtou32(buff, 0, &val);
>> + if (ret)
>> + return ret;
>> +
>> + guard(xe_pm_runtime)(dev_to_xe(dev));
>> + xe_mmio_write32(>->mmio, GT_IA_PERF_BIAS_REG, val);
>> +
>> + return count;
>> +}
>> +
>> +static struct kobj_attribute attr_gt_ia_bias = __ATTR_RW(gt_ia_bias);
>> +
>> static const struct attribute *freq_attrs[] = {
>> &attr_act_freq.attr,
>> &attr_cur_freq.attr,
>> @@ -258,8 +296,13 @@ static const struct attribute *freq_attrs[] = {
>> static void freq_fini(void *arg)
>> {
>> struct kobject *kobj = arg;
>> + struct device *dev = kobj_to_dev(kobj);
>> + struct xe_gt *gt = kobj_to_gt(kobj->parent);
>>
>> sysfs_remove_files(kobj, freq_attrs);
>> +
>> + if (xe_gt_is_main_type(gt) && !IS_DGFX(dev_to_xe(dev)))
>> + sysfs_remove_file(kobj, &attr_gt_ia_bias.attr);
>> kobject_put(kobj);
>> }
>>
>> @@ -289,6 +332,14 @@ int xe_gt_freq_init(struct xe_gt *gt)
>> return err;
>> }
>>
>> + if (xe_gt_is_main_type(gt) && !IS_DGFX(xe)) {
>> + err = sysfs_create_file(gt->freq, &attr_gt_ia_bias.attr);
>> + if (err) {
>> + kobject_put(gt->freq);
>> + return err;
>> + }
>> + }
>> +
>> err = devm_add_action_or_reset(xe->drm.dev, freq_fini, gt->freq);
>> if (err)
>> return err;
>> --
>> 2.38.1
>>
next prev parent reply other threads:[~2026-07-05 8:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-02 0:56 [PATCH v1 0/2] drm/xe: Use IBC v3 on PTL Vinay Belgaumkar
2026-07-02 0:56 ` [PATCH v1 1/2] " Vinay Belgaumkar
2026-07-03 18:31 ` Rodrigo Vivi
2026-07-02 0:56 ` [PATCH v1 2/2] drm/xe: Add sysfs for GT/IA bias Vinay Belgaumkar
2026-07-03 18:31 ` Rodrigo Vivi
2026-07-05 8:04 ` Belgaumkar, Vinay [this message]
2026-07-02 1:09 ` ✓ CI.KUnit: success for drm/xe: Use IBC v3 on PTL Patchwork
2026-07-02 2:02 ` ✓ Xe.CI.BAT: " Patchwork
2026-07-02 21:06 ` ✓ Xe.CI.FULL: " Patchwork
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