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From: Stefan Wahren <wahrenst@gmx.net>
To: Fabio Estevam <festevam@gmail.com>, Frank Li <frank.li@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	imx@lists.linux.dev,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: mx93: No cache hierachy definitions for ARM cores
Date: Fri, 19 Jul 2024 06:40:26 +0200	[thread overview]
Message-ID: <fffe2044-515c-437f-95b1-b793ba0be5aa@gmx.net> (raw)
In-Reply-To: <CAOMZO5DDk6eX+Ad9zKZmaEVvRHwFDETwuA=J7366QCRqhq_ZLw@mail.gmail.com>

Hi,

Am 19.07.24 um 04:38 schrieb Fabio Estevam:
> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
>> Hi,
>> today i noticed that imx93.dtsi lacks the cache definitions for the
>> Cortex-A55 cores:
>>
>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>
>> Maybe someone with more insight can add this to the imx93.dtsi file.
> Frank, can you help?
>
the description for caches can be found in the device tree spezification
[1]. AFAIK there is no specific binding in the kernel documentation.
Maybe a good example for reference would be [2].

Regards

[1] - https://github.com/devicetree-org/devicetree-specification
[2] -
https://elixir.bootlin.com/linux/v6.10/source/arch/arm64/boot/dts/rockchip/rk3588s.dtsi

  reply	other threads:[~2024-07-19  4:40 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-17 17:49 mx93: No cache hierachy definitions for ARM cores Stefan Wahren
2024-07-19  2:38 ` Fabio Estevam
2024-07-19  4:40   ` Stefan Wahren [this message]
2024-07-19 14:52   ` Frank Li
2024-07-24  9:48     ` Stefan Wahren
2024-07-24 14:34       ` Sudeep Holla
2024-07-24 15:55         ` Stefan Wahren
2024-08-01  2:52           ` Peng Fan

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