From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HrvwQ-00074w-D0 for qemu-devel@nongnu.org; Sat, 26 May 2007 09:04:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HrvwM-00074N-OS for qemu-devel@nongnu.org; Sat, 26 May 2007 09:04:18 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HrvwM-000747-G2 for qemu-devel@nongnu.org; Sat, 26 May 2007 09:04:14 -0400 Received: from ns.suse.de ([195.135.220.2] helo=mx1.suse.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1HrvwL-0003Tu-Js for qemu-devel@nongnu.org; Sat, 26 May 2007 09:04:14 -0400 Received: from Relay1.suse.de (mail2.suse.de [195.135.221.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id B78E71226C for ; Sat, 26 May 2007 15:04:09 +0200 (CEST) From: Andreas Schwab Date: Sat, 26 May 2007 15:04:09 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [M68K] Full extension word format addressing mode Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This patch implements the full extension word format addressing mode in the m68k emulation. I have manually verified that it gets all cases right. Andreas. Index: target-m68k/translate.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /sources/qemu/qemu/target-m68k/translate.c,v retrieving revision 1.5 diff -u -a -p -a -u -p -r1.5 target-m68k/translate.c --- target-m68k/translate.c 23 May 2007 19:58:11 -0000 1.5 +++ target-m68k/translate.c 26 May 2007 12:56:00 -0000 @@ -217,6 +217,18 @@ static int gen_ldst(DisasContext *s, int } } =20 +/* Read a 32-bit immediate constant. */ +static inline uint32_t read_im32(DisasContext *s) +{ + uint32_t im; + im =3D ((uint32_t)lduw_code(s->pc)) << 16; + s->pc +=3D 2; + im |=3D lduw_code(s->pc); + s->pc +=3D 2; + return im; +} + + /* Handle a base + index + displacement effective addresss. A base of -1 means pc-relative. */ static int gen_lea_indexed(DisasContext *s, int opsize, int base) @@ -226,41 +238,105 @@ static int gen_lea_indexed(DisasContext=20 uint16_t ext; int add; int tmp; + uint32_t bd, od; =20 offset =3D s->pc; ext =3D lduw_code(s->pc); s->pc +=3D 2; - tmp =3D ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0); - /* ??? Check W/L bit. */ - scale =3D (ext >> 9) & 3; - if (scale =3D=3D 0) { - add =3D tmp; - } else { - add =3D gen_new_qreg(QMODE_I32); - gen_op_shl32(add, tmp, gen_im32(scale)); - } - tmp =3D gen_new_qreg(QMODE_I32); - if (base !=3D -1) { - gen_op_add32(tmp, base, gen_im32((int8_t)ext)); - gen_op_add32(tmp, tmp, add); - } else { - gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext)); + if (ext & 0x100) { + /* full extension word format */ + if ((ext & 0x30) > 0x10) + /* base displacement */ + if ((ext & 0x30) =3D=3D 0x20) { + bd =3D (int16_t)lduw_code(s->pc); + s->pc +=3D 2; + } else + bd =3D read_im32(s); + else + bd =3D 0; + if ((ext & 0x40) =3D=3D 0) { + /* index not suppressed */ + add =3D ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0); + if ((ext & 0x800) =3D=3D 0) { + tmp =3D gen_new_qreg(QMODE_I32); + gen_op_ext16s32(tmp, add); + add =3D tmp; + } + scale =3D (ext >> 9) & 3; + if (scale !=3D 0) { + if ((ext & 0x800) =3D=3D 0) + tmp =3D add; + else + tmp =3D gen_new_qreg(QMODE_I32); + gen_op_shl32(tmp, add, gen_im32(scale)); + add =3D tmp; + } + } + if ((ext & 0x80) =3D=3D 0) { + /* base not suppressed */ + if (base =3D=3D -1) + tmp =3D gen_im32(offset + bd); + else if (bd !=3D 0) { + tmp =3D gen_new_qreg(QMODE_I32); + gen_op_add32(tmp, base, gen_im32(bd)); + } else + tmp =3D base; + if ((ext & 0x44) =3D=3D 0) + gen_op_add32(tmp, tmp, add); + } else if (bd !=3D 0) { + tmp =3D gen_im32(bd); + if ((ext & 0x44) =3D=3D 0) + gen_op_add32(tmp, tmp, add); + } else if ((ext & 0x44) =3D=3D 0) + tmp =3D add; + else + tmp =3D gen_im32(0); + if ((ext & 3) !=3D 0) { + /* memory indirect */ + tmp =3D gen_load(s, OS_LONG, tmp, 0); + if ((ext & 0x44) =3D=3D 4) + gen_op_add32(tmp, tmp, add); + if ((ext & 3) > 1) + /* outer displacement */ + if ((ext & 3) =3D=3D 2) { + od =3D (int16_t)lduw_code(s->pc); + s->pc +=3D 2; + } else + od =3D read_im32(s); + else + od =3D 0; + if (od !=3D 0) + gen_op_add32(tmp, tmp, gen_im32(od)); + } + } else { + /* brief extension word format */ + tmp =3D ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0); + if ((ext & 0x800) =3D=3D 0) { + add =3D gen_new_qreg(QMODE_I32); + gen_op_ext16s32(add, tmp); + tmp =3D add; + } + scale =3D (ext >> 9) & 3; + if (scale =3D=3D 0) { + add =3D tmp; + } else { + if ((ext & 0x800) =3D=3D 0) + add =3D tmp; + else + add =3D gen_new_qreg(QMODE_I32); + gen_op_shl32(add, tmp, gen_im32(scale)); + } + tmp =3D gen_new_qreg(QMODE_I32); + if (base !=3D -1) { + gen_op_add32(tmp, base, gen_im32((int8_t)ext)); + gen_op_add32(tmp, tmp, add); + } else { + gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext)); + } } return tmp; } =20 -/* Read a 32-bit immediate constant. */ -static inline uint32_t read_im32(DisasContext *s) -{ - uint32_t im; - im =3D ((uint32_t)lduw_code(s->pc)) << 16; - s->pc +=3D 2; - im |=3D lduw_code(s->pc); - s->pc +=3D 2; - return im; -} - - /* Update the CPU env CC_OP state. */ static inline void gen_flush_cc_op(DisasContext *s) { --=20 Andreas Schwab, SuSE Labs, schwab@suse.de SuSE Linux Products GmbH, Maxfeldstra=DFe 5, 90409 N=FCrnberg, Germany PGP key fingerprint =3D 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED= 5 "And now for something completely different."