From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37CD2C433E0 for ; Thu, 2 Jul 2020 14:25:57 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00EDA207D4 for ; Thu, 2 Jul 2020 14:25:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iduWrRmD" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00EDA207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Svt6k/HF85fef1QZRoHmsld8QoZ92jE8BzuICJ7scSE=; b=iduWrRmDvvs0pggUSu70yry5L u6Y0E6koa87iNsYMiGnrV87upgfYGu1nrBqlQg0/nwOZpoppsy9ewyNXhs/qJOPwqdmzukPFi868+ M1VM1zhbNcSYXGXawcOyzIjkWn4cvoTsMJ2vNe/Nz+LPe9oehx3fzoQfjEN/iC5xJNjtXdMfeuoJn qxCvkwpeHIQpZK9dsKVBHVNCowmFGpiVlViLhBEXtus7n+SnHjPqn8LRsUJHjA0UbXxLI51xVH3ed WdjckSJwmNb0tBahK3DKuZNnmNcWPFq9tXhTkJgMThnckFt1Td18HHi7KDlBiYRZ4whDBlCKHlzPC cVfoS4ePw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr08q-0007u7-4f; Thu, 02 Jul 2020 14:24:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jr08n-0007sk-3f for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2020 14:24:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 599A331B; Thu, 2 Jul 2020 07:24:37 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ABB2A3F68F; Thu, 2 Jul 2020 07:24:35 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-7-maz@kernel.org> <1f3ac757acd15f6804917e222194c9cf@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Subject: Re: [PATCH v2 06/17] irqchip/gic-v3: Configure SGIs as standard interrupts In-reply-to: <1f3ac757acd15f6804917e222194c9cf@kernel.org> Date: Thu, 02 Jul 2020 15:24:30 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_102441_232436_A2D849A8 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , Florian Fainelli , Russell King , Jason Cooper , kernel-team@android.com, Andrew Lunn , Catalin Marinas , Gregory Clement , linux-kernel@vger.kernel.org, Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 02/07/20 14:48, Marc Zyngier wrote: > On 2020-07-02 14:23, Valentin Schneider wrote: >> On 30/06/20 11:15, Marc Zyngier wrote: >>> On 2020-06-25 19:25, Valentin Schneider wrote: >>>> Also, while staring at this it dawned on me that IPI's don't need the >>>> eoimode=0 isb(): due to how the IPI flow-handler is structured, we'll >>>> get a >>>> gic_eoi_irq() just before calling into the irqaction. Dunno how much >>>> we >>>> care about it. >>> >>> That's interesting. This ISB is a leftover from the loop we had before >>> the pseudo-NMI code, where we had to make sure the write to EOIR was >>> ordered with the read from IAR. >>> >>> Given that we have an exception return right after the interrupt >>> handling, I *think* we could get rid of it (but that would need >>> mode checking on broken systems such as TX1...). I don't think >>> this is specific to IPIs though. >>> >> >> If I got this one right: >> >> 39a06b67c2c1 ("irqchip/gic: Ensure we have an ISB between ack and >> ->handle_irq") >> >> you're describing case 2, which is indeed gone on gic-v3. However IIUC >> we >> also want an ISB between poking IAR and calling into the irqaction >> (case 1) >> - we get just that with IPIs due to the early gic_eoi_irq(), but we >> don't >> for the other flows. > > You just made me realise something amazing: I've started to forget about > all this crap. Which is wonderful! ;-) > :) > More seriously, you are absolutely right. If we wanted to address this, > we'd probably have to give IPIs their own irqchip so that they get their > own eoi callback. Not sure that's worth it. > I was initially thinking of something like if (static_branch_likely(&supports_deactivate_key)) gic_write_eoir(irqnr); else if (__get_intid_range(irqnr) != SGI_RANGE) isb(); which is not particularly pretty, so maybe we should just slap this to the isb(): /* Superfluous for SGIs, but who cares */ > M. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35394C433DF for ; Thu, 2 Jul 2020 14:24:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1850220772 for ; Thu, 2 Jul 2020 14:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729826AbgGBOYi (ORCPT ); Thu, 2 Jul 2020 10:24:38 -0400 Received: from foss.arm.com ([217.140.110.172]:57178 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729437AbgGBOYi (ORCPT ); Thu, 2 Jul 2020 10:24:38 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 599A331B; Thu, 2 Jul 2020 07:24:37 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ABB2A3F68F; Thu, 2 Jul 2020 07:24:35 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-7-maz@kernel.org> <1f3ac757acd15f6804917e222194c9cf@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , Catalin Marinas , Russell King , Thomas Gleixner , Jason Cooper , Sumit Garg , Florian Fainelli , Gregory Clement , Andrew Lunn , kernel-team@android.com Subject: Re: [PATCH v2 06/17] irqchip/gic-v3: Configure SGIs as standard interrupts In-reply-to: <1f3ac757acd15f6804917e222194c9cf@kernel.org> Date: Thu, 02 Jul 2020 15:24:30 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/07/20 14:48, Marc Zyngier wrote: > On 2020-07-02 14:23, Valentin Schneider wrote: >> On 30/06/20 11:15, Marc Zyngier wrote: >>> On 2020-06-25 19:25, Valentin Schneider wrote: >>>> Also, while staring at this it dawned on me that IPI's don't need the >>>> eoimode=0 isb(): due to how the IPI flow-handler is structured, we'll >>>> get a >>>> gic_eoi_irq() just before calling into the irqaction. Dunno how much >>>> we >>>> care about it. >>> >>> That's interesting. This ISB is a leftover from the loop we had before >>> the pseudo-NMI code, where we had to make sure the write to EOIR was >>> ordered with the read from IAR. >>> >>> Given that we have an exception return right after the interrupt >>> handling, I *think* we could get rid of it (but that would need >>> mode checking on broken systems such as TX1...). I don't think >>> this is specific to IPIs though. >>> >> >> If I got this one right: >> >> 39a06b67c2c1 ("irqchip/gic: Ensure we have an ISB between ack and >> ->handle_irq") >> >> you're describing case 2, which is indeed gone on gic-v3. However IIUC >> we >> also want an ISB between poking IAR and calling into the irqaction >> (case 1) >> - we get just that with IPIs due to the early gic_eoi_irq(), but we >> don't >> for the other flows. > > You just made me realise something amazing: I've started to forget about > all this crap. Which is wonderful! ;-) > :) > More seriously, you are absolutely right. If we wanted to address this, > we'd probably have to give IPIs their own irqchip so that they get their > own eoi callback. Not sure that's worth it. > I was initially thinking of something like if (static_branch_likely(&supports_deactivate_key)) gic_write_eoir(irqnr); else if (__get_intid_range(irqnr) != SGI_RANGE) isb(); which is not particularly pretty, so maybe we should just slap this to the isb(): /* Superfluous for SGIs, but who cares */ > M.