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Wed, 30 Sep 2020 10:51:44 GMT Received: from disaster-area.hh.sledj.net (/81.187.26.238) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 30 Sep 2020 03:51:44 -0700 Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 42cceebd; Wed, 30 Sep 2020 10:51:42 +0000 (UTC) To: zhaolichang , qemu-trivial@nongnu.org Cc: zhaolichang , qemu-devel@nongnu.org Subject: Re: [PATCH RFC 03/14] riscv/: fix some comment spelling errors In-Reply-To: <20200930095321.2006-4-zhaolichang@huawei.com> References: <20200930095321.2006-1-zhaolichang@huawei.com> <20200930095321.2006-4-zhaolichang@huawei.com> X-HGTTG: heart-of-gold Sender: david.edmondson@oracle.com From: David Edmondson Date: Wed, 30 Sep 2020 11:51:42 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9759 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 spamscore=0 mlxscore=0 phishscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009300087 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9759 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 mlxscore=0 phishscore=0 suspectscore=1 mlxlogscore=999 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009300087 Received-SPF: pass client-ip=141.146.126.78; envelope-from=david.edmondson@oracle.com; helo=aserp2120.oracle.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 06:51:53 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.614, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 30 Sep 2020 10:51:45 -0400 X-BeenThere: qemu-trivial@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Sep 2020 10:51:57 -0000 On Wednesday, 2020-09-30 at 17:53:10 +08, zhaolichang wrote: > I found that there are many spelling errors in the comments of qemu/target/riscv. > I used spellcheck to check the spelling errors and found some errors in the folder. > > Signed-off-by: zhaolichang Reviewed-by: David Edmondson > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu_bits.h | 2 +- > target/riscv/csr.c | 6 +++--- > target/riscv/vector_helper.c | 2 +- > 4 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f..f40a0b2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > } else { > - qemu_log("vector verison is not specified, " > + qemu_log("vector version is not specified, " > "use the default value v0.7.1\n"); > } > set_vext_version(env, vext_version); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index bd36062..6e11555 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -536,7 +536,7 @@ > /* Leaf page shift amount */ > #define PGSHIFT 12 > > -/* Default Reset Vector adress */ > +/* Default Reset Vector address */ > #define DEFAULT_RSTVEC 0x1000 > > /* Exception causes */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 26ae347..559db11 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) > return 0; > } > > -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) > { > if (env->priv_ver < PRIV_VERSION_1_11_0) { > @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) > return 0; > } > > -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ > static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) > { > if (env->priv_ver < PRIV_VERSION_1_11_0) { > @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, > !riscv_cpu_virt_enabled(env)) { > /* > * We are in S mode without virtualisation, therefore we are in HS Mode. > - * Add 1 to the effective privledge level to allow us to access the > + * Add 1 to the effective privilege level to allow us to access the > * Hypervisor CSRs. > */ > effective_priv++; > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index a156573..fa89a6e 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, > uint32_t wd, uint32_t idx, CPURISCVState *env, > uintptr_t retaddr); > > -/* no atomic opreation for vector atomic insructions */ > +/* no atomic operation for vector atomic insructions */ > #define DO_SWAP(N, M) (M) > #define DO_AND(N, M) (N & M) > #define DO_XOR(N, M) (N ^ M) > -- > 2.26.2.windows.1 dme. -- But are you safe Miss Gradenko?