Re: [PATCH bpf-next 08/17] bpf, arm64: Add JIT support for callx

[Puranjay Mohan <puranjay@kernel.org>]

Alexei Starovoitov <alexei.starovoitov@gmail.com> writes:

> From: Alexei Starovoitov <ast@kernel.org>
>
> Emit callx as BLR to the register with the address of the subprog and
> move x0 into BPF_REG_0 like after a direct call.
>
> That's what a direct call of a subprog out of BL range is JITed into
> already. bpf functions start with BTI JC. The arguments are in x0-x7 and
> on the stack. Tail call counter ptr and private stack ptr are in callee
> saved x26 and x27.
>
> Signed-off-by: Alexei Starovoitov <ast@kernel.org>
> ---
>  arch/arm64/net/bpf_jit_comp.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
> index 6c04fee46876..9544b2f483e5 100644
> --- a/arch/arm64/net/bpf_jit_comp.c
> +++ b/arch/arm64/net/bpf_jit_comp.c
> @@ -1789,6 +1789,17 @@ static int build_insn(const struct bpf_verifier_env *env, const struct bpf_insn
>  			emit(A64_MOV(1, r0, A64_R(0)), ctx);
>  		break;
>  	}
> +	/* indirect call of a bpf subprog, dst holds its address */
> +	case BPF_JMP | BPF_CALL | BPF_X:
> +		/*
> +		 * It's the same as a direct call of a subprog that is out of
> +		 * range of BL: the subprog starts with BTI JC, the arguments
> +		 * are in place, and the registers that hold the tail call
> +		 * counter and the private stack are callee saved.
> +		 */
> +		emit(A64_BLR(dst), ctx);
> +		emit(A64_MOV(1, bpf2a64[BPF_REG_0], A64_R(0)), ctx);
> +		break;
>  	/* tail call */
>  	case BPF_JMP | BPF_TAIL_CALL:
>  		if (emit_bpf_tail_call(ctx))
> @@ -2485,6 +2496,11 @@ bool bpf_jit_supports_subprog_tailcalls(void)
>  	return true;
>  }
>  
> +bool bpf_jit_supports_callx(void)
> +{
> +	return true;
> +}
> +

Reviewed-by: Puranjay Mohan <puranjay@kernel.org>