Re: [PATCH] i386: Add missing cpu feature bits in EPYC-Rome model

[David Edmondson <dme@dme.org>]

On Tuesday, 2021-03-02 at 15:20:00 -06, Babu Moger wrote:

> Found the following cpu feature bits missing from EPYC-Rome model.
> ibrs    : Indirect Branch Restricted Speculation
> ssbd    : Speculative Store Bypass Disable
>
> These new features will be added in EPYC-Rome-v2. The -cpu help output
> after the change.
>
> x86 EPYC-Rome             (alias configured by machine type)
> x86 EPYC-Rome-v1          AMD EPYC-Rome Processor
> x86 EPYC-Rome-v2          AMD EPYC-Rome Processor
>
> Reported-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@cloud.ionos.com>
> ---
>  target/i386/cpu.c |   14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 6a53446e6a..9b5a31783d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .xlevel = 0x8000001E,
>          .model_id = "AMD EPYC-Rome Processor",
>          .cache_info = &epyc_rome_cache_info,
> +        .versions = (X86CPUVersionDefinition[]) {
> +            { .version = 1 },
> +            {
> +                .version = 2,
> +                .props = (PropValue[]) {
> +                    { "ibrs", "on" },
> +                    { "amd-ssbd", "on" },
> +                    { "model-id",
> +                      "AMD EPYC-Rome Processor" },

If the model-id isn't changing, is there any need to specify it?

> +                    { /* end of list */ }
> +                }
> +            },
> +            { /* end of list */ }
> +        }
>      },
>      {
>          .name = "EPYC-Milan",

dme.
-- 
In heaven there is no beer, that's why we drink it here.