diff for duplicates of <m2lgp19ghu.fsf@baylibre.com> diff --git a/a/1.txt b/N1/1.txt index 5fa46ed..d498b9f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ Jerome Brunet <jbrunet@baylibre.com> writes: >> based on the code from the Amlogic GPL kernel sources. Add separate >> compatibles for each SoC to make sure that we can easily implement >> all the small differences for each SoC later on. ->> +>>=20 >> In general the Meson8 and Meson8m2 seem to be almost identical as they >> even share the same mach-meson8 directory in Amlogic's GPL kernel >> sources. @@ -16,16 +16,16 @@ Jerome Brunet <jbrunet@baylibre.com> writes: >> all commented out code). >> The difference between the Meson8 and Meson8b clock gates seem to be: >> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, ->> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b +>> =C2=A0 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b >> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead ->> ? of "PERIPHS_TOP" (on Meson8b) +>> =C2=A0 of "PERIPHS_TOP" (on Meson8b) >> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or ->> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL ->> ? kernel sources) +>> =C2=A0 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL +>> =C2=A0 kernel sources) >> None of these gates is added for now, since it's unclear whether these >> definitions are actually correct (the VCLK2_ENCT gate for example is >> defined, but only used in some commented block). ->> +>>=20 >> The main difference between all three SoCs seem to be the video (VPU) >> clocks. Apart from different supported clock rates (according to vpu.c >> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the @@ -34,19 +34,28 @@ Jerome Brunet <jbrunet@baylibre.com> writes: >> (clock rate) switching. >> None of these VPU clocks are not supported by our mainline meson8b >> clock driver yet though. ->> +>>=20 >> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> >> --- ->> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++--- +>> =C2=A0.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt=C2=A0=C2=A0= +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 11 +++++++--- > -> I think you should split the binding documentation and clk changes into separate +> I think you should split the binding documentation and clk changes into s= +eparate > patches. > >> - ->> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- ->> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++- +>> =C2=A0drivers/clk/meson/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= +=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= +=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A06 +++--- +>> =C2=A0drivers/clk/meson/meson8b.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= +=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= +=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A05 ++++- > -> The change being more platform than clock related, I'd prefer if Kevin or Carlo +> The change being more platform than clock related, I'd prefer if Kevin or= + Carlo > ack it before we apply it. Acked-by: Kevin Hilman <khilman@baylibre.com> diff --git a/a/content_digest b/N1/content_digest index 3400206..73a8bf8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,22 @@ "ref\020170604183341.21417-1-martin.blumenstingl@googlemail.com\0" "ref\020170604183341.21417-2-martin.blumenstingl@googlemail.com\0" "ref\01496606325.3552.16.camel@baylibre.com\0" - "From\0khilman@baylibre.com (Kevin Hilman)\0" - "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" + "From\0Kevin Hilman <khilman@baylibre.com>\0" + "Subject\0Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Fri, 09 Jun 2017 11:13:17 -0700\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Jerome Brunet <jbrunet@baylibre.com>\0" + "Cc\0Martin Blumenstingl <martin.blumenstingl@googlemail.com>" + narmstrong@baylibre.com + linux-amlogic@lists.infradead.org + linux-clk@vger.kernel.org + mturquette@baylibre.com + sboyd@codeaurora.org + robh+dt@kernel.org + mark.rutland@arm.com + carlo@caione.org + linux@armlinux.org.uk + devicetree@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Jerome Brunet <jbrunet@baylibre.com> writes:\n" @@ -14,7 +26,7 @@ ">> based on the code from the Amlogic GPL kernel sources. Add separate\n" ">> compatibles for each SoC to make sure that we can easily implement\n" ">> all the small differences for each SoC later on.\n" - ">> \n" + ">>=20\n" ">> In general the Meson8 and Meson8m2 seem to be almost identical as they\n" ">> even share the same mach-meson8 directory in Amlogic's GPL kernel\n" ">> sources.\n" @@ -25,16 +37,16 @@ ">> all commented out code).\n" ">> The difference between the Meson8 and Meson8b clock gates seem to be:\n" ">> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,\n" - ">> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" + ">> =C2=A0 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" ">> - the gate on Meson8 for bit 7 seems to be named \"_1200XXX\" instead\n" - ">> ? of \"PERIPHS_TOP\" (on Meson8b)\n" + ">> =C2=A0 of \"PERIPHS_TOP\" (on Meson8b)\n" ">> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or\n" - ">> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" - ">> ? kernel sources)\n" + ">> =C2=A0 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" + ">> =C2=A0 kernel sources)\n" ">> None of these gates is added for now, since it's unclear whether these\n" ">> definitions are actually correct (the VCLK2_ENCT gate for example is\n" ">> defined, but only used in some commented block).\n" - ">> \n" + ">>=20\n" ">> The main difference between all three SoCs seem to be the video (VPU)\n" ">> clocks. Apart from different supported clock rates (according to vpu.c\n" ">> in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the\n" @@ -43,21 +55,30 @@ ">> (clock rate) switching.\n" ">> None of these VPU clocks are not supported by our mainline meson8b\n" ">> clock driver yet though.\n" - ">> \n" + ">>=20\n" ">> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" ">> ---\n" - ">> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---\n" + ">> =C2=A0.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt=C2=A0=C2=A0=\n" + "=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 11 +++++++---\n" ">\n" - "> I think you should split the binding documentation and clk changes into separate\n" + "> I think you should split the binding documentation and clk changes into s=\n" + "eparate\n" "> patches.\n" ">\n" ">> -\n" - ">> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---\n" - ">> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-\n" + ">> =C2=A0drivers/clk/meson/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=\n" + "=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=\n" + "=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=\n" + "=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A06 +++---\n" + ">> =C2=A0drivers/clk/meson/meson8b.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=\n" + "=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=\n" + "=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=\n" + "=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A05 ++++-\n" ">\n" - "> The change being more platform than clock related, I'd prefer if Kevin or Carlo\n" + "> The change being more platform than clock related, I'd prefer if Kevin or=\n" + " Carlo\n" "> ack it before we apply it.\n" "\n" Acked-by: Kevin Hilman <khilman@baylibre.com> -3d4fb84dbd097a70cbf4d0f74d29038b0fff90e842d64d950dc513394ea7854a +9cb28d5374fefdf5cfdcf837b6deb5c55508fd3a2316916111ded673fc133e07
diff --git a/a/content_digest b/N2/content_digest index 3400206..6568c24 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,7 +4,7 @@ "From\0khilman@baylibre.com (Kevin Hilman)\0" "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Fri, 09 Jun 2017 11:13:17 -0700\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Jerome Brunet <jbrunet@baylibre.com> writes:\n" @@ -60,4 +60,4 @@ "\n" Acked-by: Kevin Hilman <khilman@baylibre.com> -3d4fb84dbd097a70cbf4d0f74d29038b0fff90e842d64d950dc513394ea7854a +432b06682d2504e9cd75c318a4e2d7dbc1a94184ddca69e33028202e3a107fe1
diff --git a/a/1.txt b/N3/1.txt index 5fa46ed..1452272 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,4 +1,4 @@ -Jerome Brunet <jbrunet@baylibre.com> writes: +Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes: > On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote: >> The clock controller on Meson8, Meson8b and Meson8m2 is very similar @@ -16,12 +16,12 @@ Jerome Brunet <jbrunet@baylibre.com> writes: >> all commented out code). >> The difference between the Meson8 and Meson8b clock gates seem to be: >> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, ->> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b +>> CSI_DIG_CLKIN gates which don't seem to be available on Meson8b >> - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead ->> ? of "PERIPHS_TOP" (on Meson8b) +>> of "PERIPHS_TOP" (on Meson8b) >> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or ->> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL ->> ? kernel sources) +>> on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL +>> kernel sources) >> None of these gates is added for now, since it's unclear whether these >> definitions are actually correct (the VCLK2_ENCT gate for example is >> defined, but only used in some commented block). @@ -35,18 +35,22 @@ Jerome Brunet <jbrunet@baylibre.com> writes: >> None of these VPU clocks are not supported by our mainline meson8b >> clock driver yet though. >> ->> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> >> --- ->> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++--- +>> .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 11 +++++++--- > > I think you should split the binding documentation and clk changes into separate > patches. > >> - ->> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- ->> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++- +>> drivers/clk/meson/Kconfig | 6 +++--- +>> drivers/clk/meson/meson8b.c | 5 ++++- > > The change being more platform than clock related, I'd prefer if Kevin or Carlo > ack it before we apply it. -Acked-by: Kevin Hilman <khilman@baylibre.com> +Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N3/content_digest index 3400206..4b43577 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,13 +1,26 @@ "ref\020170604183341.21417-1-martin.blumenstingl@googlemail.com\0" "ref\020170604183341.21417-2-martin.blumenstingl@googlemail.com\0" "ref\01496606325.3552.16.camel@baylibre.com\0" - "From\0khilman@baylibre.com (Kevin Hilman)\0" - "Subject\0[PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" + "ref\01496606325.3552.16.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org\0" + "From\0Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH 1/3] clk: meson: meson8b: add compatibles for Meson8 and Meson8m2\0" "Date\0Fri, 09 Jun 2017 11:13:17 -0700\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Cc\0Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>" + narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org + linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" - "Jerome Brunet <jbrunet@baylibre.com> writes:\n" + "Jerome Brunet <jbrunet-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:\n" "\n" "> On Sun, 2017-06-04 at 20:33 +0200, Martin Blumenstingl wrote:\n" ">> The clock controller on Meson8, Meson8b and Meson8m2 is very similar\n" @@ -25,12 +38,12 @@ ">> all commented out code).\n" ">> The difference between the Meson8 and Meson8b clock gates seem to be:\n" ">> - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,\n" - ">> ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" + ">> \302\240 CSI_DIG_CLKIN gates which don't seem to be available on Meson8b\n" ">> - the gate on Meson8 for bit 7 seems to be named \"_1200XXX\" instead\n" - ">> ? of \"PERIPHS_TOP\" (on Meson8b)\n" + ">> \302\240 of \"PERIPHS_TOP\" (on Meson8b)\n" ">> - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or\n" - ">> ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" - ">> ? kernel sources)\n" + ">> \302\240 on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL\n" + ">> \302\240 kernel sources)\n" ">> None of these gates is added for now, since it's unclear whether these\n" ">> definitions are actually correct (the VCLK2_ENCT gate for example is\n" ">> defined, but only used in some commented block).\n" @@ -44,20 +57,24 @@ ">> None of these VPU clocks are not supported by our mainline meson8b\n" ">> clock driver yet though.\n" ">> \n" - ">> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" + ">> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>\n" ">> ---\n" - ">> ?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---\n" + ">> \302\240.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240| 11 +++++++---\n" ">\n" "> I think you should split the binding documentation and clk changes into separate\n" "> patches.\n" ">\n" ">> -\n" - ">> ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++---\n" - ">> ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-\n" + ">> \302\240drivers/clk/meson/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2406 +++---\n" + ">> \302\240drivers/clk/meson/meson8b.c\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240|\302\240\302\2405 ++++-\n" ">\n" "> The change being more platform than clock related, I'd prefer if Kevin or Carlo\n" "> ack it before we apply it.\n" "\n" - Acked-by: Kevin Hilman <khilman@baylibre.com> + "Acked-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -3d4fb84dbd097a70cbf4d0f74d29038b0fff90e842d64d950dc513394ea7854a +b003462e875502c0c3fc2b094d6a3987a1b376172a0b95582c79e440513c5215
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