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Wed, 14 May 2025 14:13:36 -0700 (PDT) Received: from ezingerman-mba ([2620:10d:c090:500::5:5d4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30e33424dbbsm2024105a91.11.2025.05.14.14.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 14:13:36 -0700 (PDT) From: Eduard Zingerman To: Kumar Kartikeya Dwivedi Cc: bpf@vger.kernel.org, Alexei Starovoitov , Andrii Nakryiko , Daniel Borkmann , Martin KaFai Lau , kkd@meta.com, kernel-team@meta.com Subject: Re: [PATCH bpf-next v2] bpf, x86: Add support for signed arena loads In-Reply-To: <20250514175415.2045783-1-memxor@gmail.com> (Kumar Kartikeya Dwivedi's message of "Wed, 14 May 2025 10:54:15 -0700") References: <20250514175415.2045783-1-memxor@gmail.com> Date: Wed, 14 May 2025 14:13:34 -0700 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Kumar Kartikeya Dwivedi writes: [...] > +static void emit_ldsx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) > +{ > + u8 *prog = *pprog; > + > + switch (size) { > + case BPF_B: > + /* movsx rax, byte ptr [rax + r12 + off] */ > + EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xBE); > + break; > + case BPF_H: > + /* movsx rax, word ptr [rax + r12 + off] */ > + EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xBF); > + break; > + case BPF_W: > + /* movsx rax, dword ptr [rax + r12 + off] */ > + EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x63); > + break; > + } > + emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); > + *pprog = prog; > +} > + I tried the following test to see what disassembly looks like: SEC("syscall") __success __arch_x86_64 __jited("movslq 0x10(%rax,%r12), %r14d") __jited("movswl 0x18(%rax,%r12), %r14d") __jited("movsbl 0x20(%rax,%r12), %r14d") __jited("movslq 0x10(%rdi,%r12), %r15d") __jited("movswl 0x18(%rdi,%r12), %r15d") __jited("movsbl 0x20(%rdi,%r12), %r15d") __naked void arena_ldsx_disasm(void *ctx) { asm volatile ( "r1 = %[arena] ll;" "r2 = 0;" "r3 = 1;" "r4 = %[numa_no_node];" "r5 = 0;" "call %[bpf_arena_alloc_pages];" "r0 = addr_space_cast(r0, 0x0, 0x1);" "r1 = r0;" "r8 = *(s32 *)(r0 + 16);" "r8 = *(s16 *)(r0 + 24);" "r8 = *(s8 *)(r0 + 32);" "r9 = *(s32 *)(r1 + 16);" "r9 = *(s16 *)(r1 + 24);" "r9 = *(s8 *)(r1 + 32);" "r0 = 0;" "exit;" :: __imm(bpf_arena_alloc_pages), __imm_addr(arena), __imm_const(numa_no_node, NUMA_NO_NODE) : __clobber_all ); } Disassembly shows instructions movslq, movswl, movsbl. While I'd expect that these shold be movslq, movswq, movsbq. (Sign extend dword/word/byte to quad word). These actually have different encodings, e.g.: 46 0f be 74 20 20 movsbl 0x20(%rax,%r12), %r14d 4e 0f be 74 20 20 movsbq 0x20(%rax,%r12), %r14 However, I can't conjure a test that shows a difference when loading and sotring values. Is this just an instruction set oddity? [...]