From: Ulrich Drepper <drepper@redhat.com>
To: root@chaos.analogic.com
Cc: kernel@kvack.org, "Dr. David Gilbert" <dg@px.uk.com>,
linux-kernel@vger.kernel.org
Subject: Re: Dual XEON - >>SLOW<< on SMP
Date: 02 Nov 2000 10:09:36 -0800 [thread overview]
Message-ID: <m3bsvy2qlb.fsf@otr.mynet.cygnus.com> (raw)
In-Reply-To: <Pine.LNX.3.95.1001102090044.8621A-100000@chaos.analogic.com>
In-Reply-To: "Richard B. Johnson"'s message of "Thu, 2 Nov 2000 09:02:38 -0500 (EST)"
"Richard B. Johnson" <root@chaos.analogic.com> writes:
> Yes. Look at the NMI count. Looks like every access produces a
> NMI.
I'm seeing this as well, but only with PIII Xeon systems, not PII
Xeon. Every single timer interrupt on any CPU is accompanied by a NMI
and LOC increment on every CPU.
CPU0 CPU1
0: 146727 153389 IO-APIC-edge timer
[...]
NMI: 300035 300035
LOC: 300028 300028
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next prev parent reply other threads:[~2000-11-02 18:10 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-11-02 13:50 Dual XEON - >>SLOW<< on SMP Dr. David Gilbert
2000-11-02 13:56 ` kernel
2000-11-02 14:02 ` Richard B. Johnson
2000-11-02 18:09 ` Ulrich Drepper [this message]
2000-11-02 18:23 ` Maciej W. Rozycki
2000-11-02 18:26 ` Matti Aarnio
2000-11-02 18:38 ` Chris Meadors
2000-11-02 18:40 ` Richard B. Johnson
2000-11-02 23:39 ` Wakko Warner
2000-11-07 22:02 ` Dr. Kelsey Hudson
2000-11-07 22:10 ` Jan-Benedict Glaw
2000-11-07 22:16 ` kernel
2000-11-07 22:31 ` Richard B. Johnson
2000-11-07 22:41 ` Keith Owens
2000-11-07 22:55 ` Richard B. Johnson
2000-11-07 23:03 ` Jeff V. Merkey
2000-11-08 14:28 ` Richard B. Johnson
2000-11-08 19:17 ` Jeff V. Merkey
2000-11-11 19:26 ` Marc Lehmann
2000-11-13 6:22 ` Jeff V. Merkey
2000-11-13 8:41 ` James A. Sutherland
2000-11-13 11:51 ` Marc Lehmann
2000-11-07 22:48 ` J . A . Magallon
2000-11-02 14:10 ` Tigran Aivazian
2000-11-02 17:39 ` Dr. David Gilbert
2000-11-03 0:04 ` bert hubert
2000-11-03 16:13 ` Ricky Beam
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