From: "Krzysztof Hałasa" <khalasa@piap.pl>
To: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: ARM64 GICv3 IRQ handling on i.MX8MP
Date: Wed, 19 Mar 2025 11:06:30 +0100 [thread overview]
Message-ID: <m3tt7pe3mh.fsf@t19.piap.pl> (raw)
In-Reply-To: <m3y0x1e4b2.fsf@t19.piap.pl> ("Krzysztof Hałasa"'s message of "Wed, 19 Mar 2025 10:51:45 +0100")
Me:
> - especially with the busy loops, the I2C IRQs appear to work in some
> sort of polled mode as well - the el1h_64_irq_handler() isn't called
> before i2c_imx_isr(). This is fast, though - ca. 1 us after the end
> of transfer.
It seems this is actually called by el0t_64_irq(), not a polling.
--
Krzysztof "Chris" Hałasa
Sieć Badawcza Łukasiewicz
Przemysłowy Instytut Automatyki i Pomiarów PIAP
Al. Jerozolimskie 202, 02-486 Warszawa
prev parent reply other threads:[~2025-03-19 10:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-19 9:51 ARM64 GICv3 IRQ handling on i.MX8MP Krzysztof Hałasa
2025-03-19 10:06 ` Krzysztof Hałasa [this message]
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