From: khalasa@piap.pl (Krzysztof Hałasa)
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-media@vger.kernel.org
Subject: Re: Suspected cache coherency problem on V4L2 and AR7100 CPU
Date: Wed, 09 Oct 2013 15:05:28 +0200 [thread overview]
Message-ID: <m3y562d27b.fsf@t19.piap.pl> (raw)
In-Reply-To: <20131009081707.GL1615@linux-mips.org> (Ralf Baechle's message of "Wed, 9 Oct 2013 10:17:07 +0200")
Ralf Baechle <ralf@linux-mips.org> writes:
> The kernel is supposed to perform the necessary cache flushing, so any
> remaining aliasing issue would be considered a bug. But the code is
> performance sensitive, some of the problem cases are twisted and complex
> so bugs and unsolved corner cases show up every now and then.
Ok. This means I should also investigate the V4L2 and the hw driver
code, because the cache aliasing shouldn't be there in the first place.
> Does it work for you, even solve your problem?
Sure, with 16 KB page size everything works fine.
--
Krzysztof Halasa
Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland
next prev parent reply other threads:[~2013-10-09 13:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-03 14:00 Suspected cache coherency problem on V4L2 and AR7100 CPU Krzysztof Hałasa
2013-10-04 8:06 ` Krzysztof Hałasa
2013-10-07 8:38 ` Krzysztof Hałasa
2013-10-07 14:24 ` Ralf Baechle
2013-10-08 8:24 ` Krzysztof Hałasa
2013-10-08 12:07 ` Ralf Baechle
2013-10-09 6:53 ` Krzysztof Hałasa
2013-10-09 8:17 ` Ralf Baechle
2013-10-09 13:05 ` Krzysztof Hałasa [this message]
2013-10-08 10:46 ` Krzysztof Hałasa
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