From: Hirofumi Fujita <h-fujita@ebina.hitachi.co.jp>
To: linux-ia64@vger.kernel.org
Subject: [Linux-ia64] kernel test10 CMCV definition
Date: Mon, 20 Nov 2000 11:07:25 +0000 [thread overview]
Message-ID: <marc-linux-ia64-105590678205752@msgid-missing> (raw)
Hi,
In test10 kernel, the definition of CMC vector register looks
different from Intel's documnet (The Itanium Architecture Software
Developer's Manual Vol. 2 rev. 1.1: System Architecture).
The order of bit fields are wrong ?
Hirofumi Fujita
Hitachi, Ltd.
--- linux-2.4.0-test10-ia64-001115/include/asm-ia64/mca.h.org Thu Nov 16 17:46:36 2000
+++ linux-2.4.0-test10-ia64-001115/include/asm-ia64/mca.h Mon Nov 20 17:23:24 2000
@@ -46,11 +46,11 @@
u64 cmcv_regval;
struct {
u64 cmcr_vector : 8;
- u64 cmcr_ignored1 : 47;
- u64 cmcr_mask : 1;
- u64 cmcr_reserved1 : 3;
- u64 cmcr_ignored2 : 1;
- u64 cmcr_reserved2 : 4;
+ u64 cmcr_reserved1 : 4;
+ u64 cmcr_ignored1 : 1;
+ u64 cmcr_reserved2 : 3;
+ u64 cmcr_mask : 1;
+ u64 cmcr_ignored2 : 47;
} cmcv_reg_s;
} cmcv_reg_t;
next reply other threads:[~2000-11-20 11:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-11-20 11:07 Hirofumi Fujita [this message]
-- strict thread matches above, loose matches on Subject: below --
2000-12-05 21:35 [Linux-ia64] kernel test10 CMCV definition David Mosberger
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