From: Keith Owens <kaos@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: Reliably creating MCA on white box Itanium-1
Date: Fri, 04 Jul 2003 01:26:37 +0000 [thread overview]
Message-ID: <marc-linux-ia64-105728237728073@msgid-missing> (raw)
In-Reply-To: <marc-linux-ia64-105721395828393@msgid-missing>
On Thu, 3 Jul 2003 08:27:36 -0500 (CDT),
Jack Steiner <steiner@sgi.com> wrote:
>>
>> Is there a way of reliably creating an MCA on a white box Itanium 1?
>> B3 processors, firmware is B117A. Failing that, what about creating an
>> MCA on a white box Itanium-2?
>>
>> Loading a duplicate ITC is no good, I need an MCA that actually enters
>> ia64_mca_ucmc_handler in mca.c. A working example using
>> PAL_CACHE_WRITE would be nice.
>
>
>Why doesnt loading a duplicate TR (not TC) work for you? I've used that
>method and found it to be reliable.
Because mca_asm.S does not call the C code for TLB errors. I want to
test the C code on standard hardware.
next prev parent reply other threads:[~2003-07-04 1:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-03 6:29 Reliably creating MCA on white box Itanium-1 Keith Owens
2003-07-03 13:27 ` Jack Steiner
2003-07-04 1:26 ` Keith Owens [this message]
2003-07-04 1:42 ` Jack Steiner
2003-07-04 12:56 ` Grant Grundler
2003-07-09 15:27 ` Luck, Tony
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