From: "Choi, Youngsoo" <youngsoo.choi@intel.com>
To: linux-ia64@vger.kernel.org
Subject: RE: IA-64 instruction latencies
Date: Wed, 16 Jul 2003 15:57:35 +0000 [thread overview]
Message-ID: <marc-linux-ia64-105837199511214@msgid-missing> (raw)
In-Reply-To: <marc-linux-ia64-105836975208054@msgid-missing>
Hi,
For Itanium2
http://www.intel.com/design/itanium2/manuals/251110.htm
page 17
For Itanium
http://www.intel.com/design/itanium/downloads/245474.htm
page 9-12
For all the manuals,
http://www.intel.com/design/itanium/manuals.htm
For more information about optimization, there is a document, "Introduction to Microarchitectural Optimization for Itanium 2 Processors", available on the Intel Developer Services web site http://cedar.intel.com/cgi-bin/ids.dll/topic.jsp?catCode=BMC
-------
Youngsoo Choi
EPD Architecture Team Tel.: (408) 653-8970
Intel Corporation Loc.: SC12/3rd/Pole L2
-----Original Message-----
From: CH Gowri Kumar [mailto:gkumar@csa.iisc.ernet.in]
Sent: Wednesday, July 16, 2003 8:31 AM
To: linux-ia64@vger.kernel.org
Subject: IA-64 instruction latencies
Hello All,
I am unable to find a document which gives the latencies of the different
instructions of Itanium instruction set. Can anyone point me to such a
document?
Regards,
Gowri Kumar
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next prev parent reply other threads:[~2003-07-16 15:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-16 15:42 IA-64 instruction latencies CH Gowri Kumar
2003-07-16 15:57 ` Choi, Youngsoo [this message]
2003-07-16 17:28 ` David Mosberger
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