From: Jack Steiner <steiner@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: 4 SGI patches - non-identity mapped kernel + misc fixes
Date: Sun, 31 Aug 2003 13:31:53 +0000 [thread overview]
Message-ID: <marc-linux-ia64-106233674100576@msgid-missing> (raw)
Bjorn -
Attached are 4 patches for the SGI platform. These are against the latest
2.4 bitkeeper tree.
The patches:
linux/arch/ia64/config.in
- delete some remnents of support for the SGI SN1 platform
- add config option for SN2.
linux_base/arch/ia64/kernel/Makefile
- fix compile error (SN2 needs iosapic.o)
linux/arch/ia64/acpi.c
- update acpi.c to recognize the SN2 platform
linux/arch/ia64/kernel/efi_stub.S
linux/arch/ia64/kernel/head.S
linux/arch/ia64/kernel/pal.S
- backport of 2.6 "ia64_switch_mode" changes for non-identity
mapped kernels
--------------------------------------------------------------------------------------
linux/arch/ia64/config.in | 12 +-----
linux/arch/ia64/kernel/Makefile | 1
linux/arch/ia64/kernel/acpi.c | 5 +-
linux/arch/ia64/kernel/efi_stub.S | 4 +-
linux/arch/ia64/kernel/head.S | 74 +++++++++++++++++++++++++++++++-------
linux/arch/ia64/kernel/pal.S | 10 ++---
6 files changed, 76 insertions(+), 30 deletions(-)
diff -Naur linux_base/arch/ia64/config.in linux/arch/ia64/config.in
--- linux_base/arch/ia64/config.in Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/config.in Fri Aug 29 08:26:14 2003
@@ -35,7 +35,6 @@
DIG-compliant CONFIG_IA64_DIG \
HP-simulator CONFIG_IA64_HP_SIM \
HP-zx1 CONFIG_IA64_HP_ZX1 \
- SGI-SN1 CONFIG_IA64_SGI_SN1 \
SGI-SN2 CONFIG_IA64_SGI_SN2" generic
if [ "$CONFIG_ITANIUM" = "y" ]; then
@@ -54,11 +53,7 @@
if [ "$CONFIG_ITANIUM" = "y" ]; then
define_bool CONFIG_IA64_BRL_EMU y
bool ' Enable Itanium B-step specific code' CONFIG_ITANIUM_BSTEP_SPECIFIC
- if [ "$CONFIG_IA64_SGI_SN1" = "y" ]; then
- define_int CONFIG_IA64_L1_CACHE_SHIFT 7 # align cache-sensitive data to 128 bytes
- else
- define_int CONFIG_IA64_L1_CACHE_SHIFT 6 # align cache-sensitive data to 64 bytes
- fi
+ define_int CONFIG_IA64_L1_CACHE_SHIFT 6 # align cache-sensitive data to 64 bytes
fi
if [ "$CONFIG_MCKINLEY" = "y" ]; then
@@ -74,13 +69,12 @@
define_bool CONFIG_PM y
fi
-if [ "$CONFIG_IA64_SGI_SN1" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
+if [ "$CONFIG_IA64_SGI_SN2" = "y" ]; then
define_bool CONFIG_IA64_SGI_SN y
bool ' Enable extra debugging code' CONFIG_IA64_SGI_SN_DEBUG
bool ' Enable SGI Medusa Simulator Support' CONFIG_IA64_SGI_SN_SIM
- bool ' Enable autotest (llsc). Option to run cache test instead of booting' \
- CONFIG_IA64_SGI_AUTOTEST
bool ' Enable protocol mode for the L1 console' CONFIG_SERIAL_SGI_L1_PROTOCOL
+ define_bool CONFIG_HWGFS_FS y
define_bool CONFIG_DISCONTIGMEM y
define_bool CONFIG_IA64_MCA y
define_bool CONFIG_NUMA y
diff -Naur linux_base/arch/ia64/kernel/Makefile linux/arch/ia64/kernel/Makefile
--- linux_base/arch/ia64/kernel/Makefile Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/kernel/Makefile Thu Aug 28 12:15:00 2003
@@ -17,6 +17,7 @@
machvec.o pal.o process.o perfmon.o ptrace.o sal.o salinfo.o semaphore.o setup.o \
signal.o sys_ia64.o traps.o time.o unaligned.o unwind.o
obj-$(CONFIG_IA64_GENERIC) += iosapic.o
+obj-$(CONFIG_IA64_SGI_SN2) += iosapic.o
obj-$(CONFIG_IA64_HP_ZX1) += iosapic.o
obj-$(CONFIG_IA64_DIG) += iosapic.o
obj-$(CONFIG_IA64_PALINFO) += palinfo.o
diff -Naur linux_base/arch/ia64/kernel/acpi.c linux/arch/ia64/kernel/acpi.c
--- linux_base/arch/ia64/kernel/acpi.c Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/kernel/acpi.c Thu Aug 28 12:15:00 2003
@@ -98,6 +98,9 @@
if (!strcmp(hdr->oem_id, "HP")) {
return "hpzx1";
}
+ else if (!strcmp(hdr->oem_id, "SGI")) {
+ return "sn2";
+ }
return "dig";
#else
@@ -105,8 +108,6 @@
return "hpsim";
# elif defined (CONFIG_IA64_HP_ZX1)
return "hpzx1";
-# elif defined (CONFIG_IA64_SGI_SN1)
- return "sn1";
# elif defined (CONFIG_IA64_SGI_SN2)
return "sn2";
# elif defined (CONFIG_IA64_DIG)
diff -Naur linux_base/arch/ia64/kernel/efi_stub.S linux/arch/ia64/kernel/efi_stub.S
--- linux_base/arch/ia64/kernel/efi_stub.S Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/kernel/efi_stub.S Thu Aug 28 20:17:38 2003
@@ -62,7 +62,7 @@
mov b6=r2
;;
andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
- br.call.sptk.many rp=ia64_switch_mode
+ br.call.sptk.many rp=ia64_switch_mode_phys
.ret0: mov out4=in5
mov out0=in1
mov out1=in2
@@ -73,7 +73,7 @@
br.call.sptk.many rp¶ // call the EFI function
.ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode
mov r16=loc3
- br.call.sptk.many rp=ia64_switch_mode // return to virtual mode
+ br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
.ret2: mov ar.rsc=loc4 // restore RSE configuration
mov ar.pfs=loc1
mov rp=loc0
diff -Naur linux_base/arch/ia64/kernel/head.S linux/arch/ia64/kernel/head.S
--- linux_base/arch/ia64/kernel/head.S Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/kernel/head.S Thu Aug 28 20:16:41 2003
@@ -725,7 +725,7 @@
*
* Note: RSE must already be in enforced lazy mode
*/
-GLOBAL_ENTRY(ia64_switch_mode)
+GLOBAL_ENTRY(ia64_switch_mode_phys)
{
alloc r2=ar.pfs,0,0,0,0
rsm psr.i | psr.ic // disable interrupts and interrupt collection
@@ -735,36 +735,86 @@
{
flushrs // must be first insn in group
srlz.i
- shr.u r19=r15,61 // r19 <- top 3 bits of current IP
}
;;
mov cr.ipsr=r16 // set new PSR
- add r3\x1f-ia64_switch_mode,r15
- xor r15=0x7,r19 // flip the region bits
+ add r3\x1f-ia64_switch_mode_phys,r15
mov r17=ar.bsp
mov r14=rp // get return address into a general register
+ ;;
- // switch RSE backing store:
+ // going to physical mode, use tpa to translate virt->phys
+ tpa r17=r17
+ tpa r3=r3
+ tpa sp=sp
+ tpa r14=r14
;;
- dep r17=r15,r17,61,3 // make ar.bsp physical or virtual
+
mov r18=ar.rnat // save ar.rnat
- ;;
mov ar.bspstore=r17 // this steps on ar.rnat
- dep r3=r15,r3,61,3 // make rfi return address physical or virtual
- ;;
mov cr.iip=r3
mov cr.ifs=r0
- dep sp=r15,sp,61,3 // make stack pointer physical or virtual
;;
mov ar.rnat=r18 // restore ar.rnat
- dep r14=r15,r14,61,3 // make function return address physical or virtual
rfi // must be last insn in group
;;
1: mov rp=r14
br.ret.sptk.many rp
-END(ia64_switch_mode)
+END(ia64_switch_mode_phys)
+/*
+ * Switch execution mode from physical to virtual
+ *
+ * Inputs:
+ * r16 = new psr to establish
+ *
+ * Note: RSE must already be in enforced lazy mode
+ */
+GLOBAL_ENTRY(ia64_switch_mode_virt)
+ {
+ alloc r2=ar.pfs,0,0,0,0
+ rsm psr.i | psr.ic // disable interrupts and interrupt collection
+ mov r15=ip
+ }
+ ;;
+ {
+ flushrs // must be first insn in group
+ srlz.i
+ }
+ ;;
+ mov cr.ipsr=r16 // set new PSR
+ add r3\x1f-ia64_switch_mode_virt,r15
+
+ mov r17=ar.bsp
+ mov r14=rp // get return address into a general register
+ ;;
+
+ // going to virtual
+ // - for code addresses, set upper bits of addr to KERNEL_START
+ // - for stack addresses, set upper 3 bits to 0xe.... Dont change any of the
+ // lower bits since we want it to stay identity mapped
+ movl r18=KERNEL_START
+ dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
+ dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
+ dep r17=-1,r17,61,3
+ dep sp=-1,sp,61,3
+ ;;
+ or r3=r3,r18
+ or r14=r14,r18
+ ;;
+
+ mov r18=ar.rnat // save ar.rnat
+ mov ar.bspstore=r17 // this steps on ar.rnat
+ mov cr.iip=r3
+ mov cr.ifs=r0
+ ;;
+ mov ar.rnat=r18 // restore ar.rnat
+ rfi // must be last insn in group
+ ;;
+1: mov rp=r14
+ br.ret.sptk.many rp
+END(ia64_switch_mode_virt)
#ifdef CONFIG_IA64_BRL_EMU
/*
diff -Naur linux_base/arch/ia64/kernel/pal.S linux/arch/ia64/kernel/pal.S
--- linux_base/arch/ia64/kernel/pal.S Thu Aug 28 11:56:41 2003
+++ linux/arch/ia64/kernel/pal.S Fri Aug 29 10:58:52 2003
@@ -164,7 +164,7 @@
;;
mov loc4=ar.rsc // save RSE configuration
dep.z loc2=loc2,0,61 // convert pal entry point to physical
- dep.z r8=r8,0,61 // convert rp to physical
+ tpa r8=r8 // convert rp to physical
;;
mov b7 = loc2 // install target to branch reg
mov ar.rsc=0 // put RSE in enforced lazy, LE mode
@@ -174,13 +174,13 @@
or loc3=loc3,r17 // add in psr the bits to set
;;
andcm r16=loc3,r16 // removes bits to clear from psr
- br.call.sptk.many rp=ia64_switch_mode
+ br.call.sptk.many rp=ia64_switch_mode_phys
.ret1: mov rp = r8 // install return address (physical)
br.cond.sptk.many b7
1:
mov ar.rsc=0 // put RSE in enforced lazy, LE mode
mov r16=loc3 // r16= original psr
- br.call.sptk.many rp=ia64_switch_mode // return to virtual mode
+ br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
.ret2:
mov psr.l = loc3 // restore init PSR
@@ -228,13 +228,13 @@
mov b7 = loc2 // install target to branch reg
;;
andcm r16=loc3,r16 // removes bits to clear from psr
- br.call.sptk.many rp=ia64_switch_mode
+ br.call.sptk.many rp=ia64_switch_mode_phys
.ret6:
br.call.sptk.many rp· // now make the call
.ret7:
mov ar.rsc=0 // put RSE in enforced lazy, LE mode
mov r16=loc3 // r16= original psr
- br.call.sptk.many rp=ia64_switch_mode // return to virtual mode
+ br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
.ret8: mov psr.l = loc3 // restore init PSR
mov ar.pfs = loc1
--
Thanks
Jack Steiner (steiner@sgi.com) 651-683-5302
Principal Engineer SGI - Silicon Graphics, Inc.
next reply other threads:[~2003-08-31 13:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-08-31 13:31 Jack Steiner [this message]
-- strict thread matches above, loose matches on Subject: below --
2003-09-04 15:05 4 SGI patches - non-identity mapped kernel + misc fixes Bjorn Helgaas
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