Re: Ultra AXmp

[Bob Drzyzgula <bob@drzyzgula.org>]

On Wed, Jul 15, 1998 at 02:07:05AM -0600, Ward Deng wrote:
> > 
> > I thought the real claim to fame of all of Sun's multiprocessing
> > systems (and the SP2, and the Power Challenge, and the...) has always
> > been their really fast/expensive IPC bus, not their interface to
>                                    ^^^^^^^
> What do you mean that?

I belive that, in the case of the UltraSPARC, it would
refer to the Ultra Port Architecture (UPA), which
provides a point-to-point packet switched interconnect
for processors, memory and I/O. The UPA has special
accelerators for the cache coherancy mechanism, and
supports device connections with various bitwidths.
At over four processors, the UPA gets extended into
a more distributed architecture called the gigaplane.

Personally, I would rather that Sun had a distributed
memory machine... the UltraSPARC machines have per-CPU
cache but not per-CPU DRAM. I believe that the
UltraSPARC III specifically does provide for per-CPU
DRAM; I don't know excactly how that would be implemented
in a system architecture or OS-wise.

--Bob

See:
http://www.sun.com/microelectronics/whitepapers/wp95-023.html.
http://wwwwseast2.usec.sun.com/servers/enterprise/10000/Tour/interconnect.html
http://wwwwseast2.usec.sun.com/servers/enterprise/10000/wp/E10000.pdf


-- 
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Bob Drzyzgula                             It's not a problem
bob@drzyzgula.org                until something bad happens
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