From: "David S. Miller" <davem@dm.cobaltmicro.com>
To: ultralinux@vger.kernel.org
Subject: Re: VIS
Date: Fri, 17 Jul 1998 12:46:54 +0000 [thread overview]
Message-ID: <marc-linux-ultrasparc-90222358531056@msgid-missing> (raw)
In-Reply-To: <marc-linux-ultrasparc-90222358531047@msgid-missing>
Date: Fri, 17 Jul 1998 14:44:39 +0200
From: Andi Kleen <ak@muc.de>
But how does it know what CPU units are used by the inline
assembly? It does not make much sense to schedule without knowing
that.
GCC doesn't get perfect scheduling in any event. And it won't for
some time until real superscalar facilities are added.
What the current gcc scheduler does do very well is seperate memory
references from their first usage, and inter-insn register dependancy
seperation. With my proposed scheme, you'll get that for inline asm.
It will also fill delay slots in reorg with these asms, which a lot of
the time on Sparc is extremely important.
Later,
David S. Miller
davem@dm.cobaltmicro.com
next prev parent reply other threads:[~1998-07-17 12:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
1998-07-16 12:23 VIS Sven Grundmann
1998-07-16 12:27 ` VIS David S. Miller
1998-07-16 13:12 ` VIS Sven Grundmann
1998-07-16 13:26 ` VIS David S. Miller
1998-07-16 23:37 ` VIS Andi Kleen
1998-07-17 3:58 ` VIS David S. Miller
1998-07-17 11:22 ` VIS Andi Kleen
1998-07-17 12:34 ` VIS David S. Miller
1998-07-17 12:44 ` VIS Andi Kleen
1998-07-17 12:46 ` David S. Miller [this message]
1998-07-17 13:29 ` VIS Andi Kleen
1998-07-17 13:42 ` VIS David S. Miller
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