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Mon, 18 May 2026 19:32:46 -0700 (PDT) From: Ritesh Harjani (IBM) To: Sayali Patil , linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com Cc: linux-kernel@vger.kernel.org, Mahesh Salgaonkar Subject: Re: [PATCH v2 1/2] lkdtm/powerpc: add isync after slbmte to enforce SLB update ordering In-Reply-To: <2f8d430962a96a7498903b994f081deee4a4d97a.1778975974.git.sayalip@linux.ibm.com> Date: Tue, 19 May 2026 07:54:38 +0530 Message-ID: References: <2f8d430962a96a7498903b994f081deee4a4d97a.1778975974.git.sayalip@linux.ibm.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list Sayali Patil writes: > The slbmte instruction modifies the Segment Lookaside Buffer, but without > a context synchronizing operation the CPU is not guaranteed to observe > the updated SLB state for subsequent instructions. This can result in > use of stale translation state when memory is accessed immediately after > SLB modifications. > > Add isync after each slbmte in the PPC_SLB_MULTIHIT test to ensure proper > ordering of SLB updates before subsequent memory accesses. > > This aligns with Power ISA context synchronization requirements for changes > in address translation state and improves the reliability of SLB multihit > injection tests in hash MMU mode. > Yup, CSI is required for before & after a slbmte. Given we are trying to add duplicate slb entries, I think the isync()s added in this patch is sufficient. LGTM. Feel free to add: Reviewed-by: Ritesh Harjani (IBM) As Mpe added - This needs to be cc'd to Kees. -> ./scripts/get_maintainer.pl -f drivers/misc/lkdtm/powerpc.c Kees Cook (maintainer:LINUX KERNEL DUMP TEST MODULE (LKDTM)) Arnd Bergmann (maintainer:CHAR and MISC DRIVERS) Greg Kroah-Hartman (maintainer:CHAR and MISC DRIVERS) linux-kernel@vger.kernel.org (open list) CHAR and MISC DRIVERS status: Supported -ritesh