From: Andreas Schwab <schwab@suse.de>
To: Alistair Francis <alistair23@gmail.com>
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Michael Clark" <mjc@sifive.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue
Date: Tue, 10 Jul 2018 09:25:09 +0200 [thread overview]
Message-ID: <mvmr2kb5z8q.fsf@suse.de> (raw)
In-Reply-To: <CAKmqyKNx9M6rLGcrv-ZuCtf5q5QyjrdpNr5d+q=tAdqZSXvJRQ@mail.gmail.com> (Alistair Francis's message of "Mon, 9 Jul 2018 14:52:31 -0700")
On Jul 09 2018, Alistair Francis <alistair23@gmail.com> wrote:
> On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab <schwab@suse.de> wrote:
>> What is the state of the sifive_u emulation? When I tried to boot a bbl
>> with an included kernel I get these errors:
>>
>> qemu-system-riscv64: plic: invalid register write: 00002090
>> qemu-system-riscv64: plic: invalid register write: 00002094
>> qemu-system-riscv64: plic: invalid register write: 00002098
>> qemu-system-riscv64: plic: invalid register write: 0000209c
>> qemu-system-riscv64: plic: invalid register write: 000020a0
>> qemu-system-riscv64: plic: invalid register write: 000020a4
>> qemu-system-riscv64: plic: invalid register write: 000020a8
>> qemu-system-riscv64: plic: invalid register write: 000020ac
>> qemu-system-riscv64: plic: invalid register write: 000020b0
>> qemu-system-riscv64: plic: invalid register write: 000020b4
>
> I see those as well. I haven't investigated but I assume we are just
> not completely modelling the PLIC. In saying that it should still
> boot. Do you not see the kernel booting?
I don't see those errors when using the qemu from github:riscv/riscv-qemu.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
next prev parent reply other threads:[~2018-07-10 7:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-06 1:22 [Qemu-devel] [PULL v4 0/7] riscv-pull queue Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 2/7] hw/riscv/sifive_e: Create a SiFive E " Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 5/7] hw/riscv/sifive_u: Set the interrupt controller number of interrupts Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ Alistair Francis
2018-07-06 1:22 ` [Qemu-devel] [PULL v4 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device Alistair Francis
2018-07-06 10:13 ` [Qemu-devel] [PULL v4 0/7] riscv-pull queue Peter Maydell
2018-07-09 10:00 ` Andreas Schwab
2018-07-09 21:52 ` Alistair Francis
2018-07-09 23:04 ` Michael Clark
2018-08-03 1:58 ` Palmer Dabbelt
2018-07-10 7:25 ` Andreas Schwab [this message]
2018-07-11 0:09 ` Alistair Francis
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