[ovmf baseline-only test] 38318: all pass

[Platform Team regression test user <citrix-osstest@xenproject.org>]

This run is configured for baseline tests only.

flight 38318 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/38318/

Perfect :-)
All tests in this flight passed
version targeted for testing:
 ovmf                 55df704dd24928b60b10bbb9dec5bfa7682910de
baseline version:
 ovmf                 386cdfbecbbacb600ffc8e2ffa8c7af1b3855a61

Last test of basis    38308  2015-11-19 04:24:18 Z    1 days
Testing same since    38318  2015-11-20 17:23:41 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Ard Biesheuvel <ard.biesheuvel@linaro.org>
  Hess Chen <hesheng.chen@intel.com>
  Ruiyu Ni <ruiyu.ni@intel.com>
  Star Zeng <star.zeng@intel.com>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 55df704dd24928b60b10bbb9dec5bfa7682910de
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 16:18:40 2015 +0000

    ArmPkg/ArmV7Mmu: handle memory regions over 4 GB correctly
    
    The ARM_MEMORY_REGION_DESCRIPTOR array provided by the platform may
    contain entries that extend beyond the 4 GB boundary, above which
    we can't map anything on 32-bit ARM. If this is the case, map only
    the 1:1 addressable part.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18900 6f19259b-4bc3-4df7-8a09-765794883524

commit 72143137f4ea558757cb7933b1f3a0c21252126b
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:59:59 2015 +0000

    ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBR
    
    Bits 0 and 6 of the TTBRx system registers have different meanings
    depending on whether a system implements the Multiprocessing
    Extensions. So use separate memory attribute definitions for MP and
    non-MP.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524

commit 42dc8026a8711315652936ffd334a4752bbd5d2e
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:59:42 2015 +0000

    ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLE
    
    The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not
    bit 0 set. Furthermore, the name is inconsistent with the other definitions
    so rename it to TTBR_INNER_NON_CACHEABLE.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524

commit 65ceda9173e688a42a3e74c0c94f4dffc569029c
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:59:22 2015 +0000

    ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareable
    
    Even though mapping normal memory (inner) shareable is usually the
    correct choice on coherent systems, it may be desirable in some cases
    to use non-shareable mappings for normal memory, e.g., when hardware
    managed coherency is not required and the memory system is not fully
    configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride
    that makes cacheable mappings of normal memory non-shareable.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18897 6f19259b-4bc3-4df7-8a09-765794883524

commit 07070ecc76cff00175715f9a9534bc9216599a11
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:59:04 2015 +0000

    ArmPkg/ArmV7Mmu: make cached translation table accesses shareable
    
    To align with the way normal cacheable memory is mapped, set the
    shareable bit for cached accesses performed by the page table walker.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524

commit 2ea66ed9f9ea18cbe2681baaad29ce47ea9918a1
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:58:46 2015 +0000

    ArmPkg/ArmV7Lib: add function to test for presence of MP extensions
    
    Some MMU manipulation is dependent on the presence of the multiprocessing
    extensions. So add a function that returns this information.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18895 6f19259b-4bc3-4df7-8a09-765794883524

commit 63dbd629649a4c5ccf83243e9482a4e0d092b422
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:58:26 2015 +0000

    ArmPkg/ArmV7Lib: add support for reading the ID_MMFR0 system register
    
    Implement an accessor function for the ID_MMFR0 system register, which
    contains information about the VMSA implementation. We will need this
    to access the number of shareability levels and the nature of their
    implementations.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18894 6f19259b-4bc3-4df7-8a09-765794883524

commit a6ec831c10d7994098e100b441a96bbe735dda01
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 15:58:03 2015 +0000

    ArmPkg/ArmV7Mmu: fix write-through translation table accesses
    
    The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since
    a) its meaning is unclear in the context of TTBRx, since write through
       always implies Read-Allocate and no Write-Allocate
    b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC
    
    So instead, rename it to TTBR_WRITE_THROUGH and update the definition
    to reflect the name.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524

commit 6bc35cbaca790fc32904cbb4f1bfc30381910ed0
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 11:51:06 2015 +0000

    ArmPkg/Mmu: set required XN attributes for device mappings
    
    To prevent speculative intruction fetches from MMIO ranges that may
    have side effects on reads, the architecture requires device mappings
    to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and
    EL1&0 translation regimes, respectively.)
    
    Note that, in the ARM case, this involves moving all accesses to a
    client domain since permission attributes like XN are ignored from
    a manager domain. The use of a client domain is actually mandated
    explicitly by the UEFI spec.
    
    Reported-by: Heyi Guo <heyi.guo@linaro.org>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524

commit 19bb46c411279dcd30d540c56e5993c5f771c319
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 11:50:50 2015 +0000

    ArmVExpressPkg/ArmVExpressLibRTSM: map NOR flash as normal memory
    
    Some users of this library (i.e., FVP-AArch64 and RTSM-A15_MPCore)
    may be built to execute straight from NOR flash. Since device mappings
    should have the XN attribute set (according to the architecture), mapping
    the NOR flash as a device may prevent it from being executable.
    
    Since the NOR flash DXE driver is perfectly capable of setting the correct
    attributes for the region it needs to write to, and since we will be
    executing from DRAM by that time anyway, we can simply map the NOR flash
    as normal memory initially.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18890 6f19259b-4bc3-4df7-8a09-765794883524

commit dca7f96fd246130cfa7ffa29aa81e0d956ed413b
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 11:50:33 2015 +0000

    ArmVirtPkg/ArmVirtPlatformLib: map executable NOR region as normal memory
    
    The ARM architecture version 7 and later mandates that device mappings
    have the XN (non-executable) bit set, to prevent speculative instruction
    fetches from read-sensitive regions. This implies that we should not map
    regions as device if we want to execute from them, so the NOR region that
    contains our FD image should be mapped as normal memory instead.
    
    The MMU code deals correctly with overlapping ARM_MEMORY_REGION_DESCRIPTOR
    entries, and later entries in the array take precedence over earlier ones.
    So simply add an entry to the end of the array that overrides the mapping
    attributes of the FD image, wherever it resides.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Laszlo Ersek <lersek@redhat.com>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18889 6f19259b-4bc3-4df7-8a09-765794883524

commit dd7a987dac8526fbd9605e5ae3da6d396f5bf6f4
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Nov 18 11:50:12 2015 +0000

    ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()
    
    The function GcdAttributeToArmAttribute() is not used anywhere in the
    code base, and is only defined for AARCH64 and not for ARM. It also
    fails to set the bits for shareability and non-executability that we
    require for correct operation. So remove it.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18888 6f19259b-4bc3-4df7-8a09-765794883524

commit 305d3c8e8da4b0bb0f3f8d216d8ac91fe33d5464
Author: Star Zeng <star.zeng@intel.com>
Date:   Wed Nov 18 10:13:31 2015 +0000

    MdeModulePkg PeiCore: PeiInstallPeiMemory improper ASSERT test on second call
    
    The ASSERT (PrivateData->PeiMemoryInstalled) in if (PrivateData->PeiMemoryInstalled)
    condition is useless, it should be ASSERT (FALSE) to follow the code's expectation.
    
    Cc: Liming Gao <liming.gao@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Star Zeng <star.zeng@intel.com>
    Reviewed-by: Liming Gao <liming.gao@intel.com>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18887 6f19259b-4bc3-4df7-8a09-765794883524

commit 48b77f5ea9091d78098ba0d6168d4b638914f280
Author: Hess Chen <hesheng.chen@intel.com>
Date:   Wed Nov 18 05:38:35 2015 +0000

    BaseTool/UPT: Add supporting of decimal numbers for INF_VERSION and DEC_SPECIFICATION
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Hess Chen <hesheng.chen@intel.com>
    Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
    
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18868 6f19259b-4bc3-4df7-8a09-765794883524

commit b9335cf562f11a096efea6c98d8612f22929eeb9
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Wed Nov 18 05:05:22 2015 +0000

    MdeModulePkg: Change BootLogoEnableLogo use INTN for minus value
    
    The parameter name is also changed from Coordinate* to Offset* to
    reflect that it's the offset to the location specified by Attribute.
    For example, when the Attribute is Center, OffsetX and OffsetY are
    used to specify the offset to the Center. OffsetX = 100 means
    100 pixels right to the Center.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Feng Tian <feng.tian@intel.com>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18867 6f19259b-4bc3-4df7-8a09-765794883524

commit c25be72e15b9f499551278b06b458c5bf072646f
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Wed Nov 18 05:04:23 2015 +0000

    MdeModulePkg: Change PlatformLogo.GetImage use INTN for minus value
    
    The parameter name is also changed from Coordinate* to Offset* to
    reflect that it's the offset to the location specified by Attribute.
    For example, when the Attribute is Center, OffsetX and OffsetY are
    used to specify the offset to the Center. OffsetX = 100 means
    100 pixels right to the Center.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Feng Tian <feng.tian@intel.com>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18866 6f19259b-4bc3-4df7-8a09-765794883524