From: Platform Team regression test user <citrix-osstest@xenproject.org>
To: xen-devel@lists.xensource.com, osstest-admin@xenproject.org
Subject: [ovmf baseline-only test] 38321: all pass
Date: Sun, 22 Nov 2015 05:52:43 +0000 [thread overview]
Message-ID: <osstest-38321-mainreport@xen.org> (raw)
This run is configured for baseline tests only.
flight 38321 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/38321/
Perfect :-)
All tests in this flight passed
version targeted for testing:
ovmf 3b1495156a3576992b31a77e799db207cb61d9de
baseline version:
ovmf 55df704dd24928b60b10bbb9dec5bfa7682910de
Last test of basis 38318 2015-11-20 17:23:41 Z 1 days
Testing same since 38321 2015-11-22 03:49:53 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Cecil Sheng <cecil.sheng@hpe.com>
Jeff Fan <jeff.fan@intel.com>
Jordan Justen <jordan.l.justen@intel.com>
Leif Lindholm <leif.lindholm@linaro.org>
Mark Rutland <mark.rutland@arm.com>
Star Zeng <star.zeng@intel.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Push not applicable.
------------------------------------------------------------
commit 3b1495156a3576992b31a77e799db207cb61d9de
Author: Leif Lindholm <leif.lindholm@linaro.org>
Date: Fri Nov 20 13:14:59 2015 +0000
ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias
In ArmLib, there exists an alias for ArmDataSynchronizationBarrier,
named after one of several names for the pre-ARMv6 cp15 operation that
was formalised into the Data Synchronization Barrier in ARMv6.
This alias is also the one called from within ArmLib, in preference of
the correct name. Through the power of code reuse, this name slipped
into the AArch64 variant as well.
Expunge it from the codebase.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
commit f73dd6f5bb31aed6097bcb4991fc04b542fc3911
Author: Jordan Justen <jordan.l.justen@intel.com>
Date: Fri Nov 20 08:22:46 2015 +0000
UefiCpuPkg/CpuDxe: Don't use gBS->Stall
The CpuDxe driver may run before the gEfiMetronomeArchProtocolGuid
protocol is installed. gBS->Stall does not work until this arch
protocol is installed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18914 6f19259b-4bc3-4df7-8a09-765794883524
commit 02018760ca5eaeb5676a86784d724599369d5b52
Author: Star Zeng <star.zeng@intel.com>
Date: Fri Nov 20 01:51:15 2015 +0000
MdeModulePkg BaseSerialPortLib16550: Fix typo in SerialPortWrite()
The "read" word in SerialPortWrite() header comment block should be
"write".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18910 6f19259b-4bc3-4df7-8a09-765794883524
commit 091a12620b17b2aada4b76f77d7926fe33b93128
Author: Star Zeng <star.zeng@intel.com>
Date: Fri Nov 20 01:50:34 2015 +0000
PcAtChipsetPkg SerialIoLib: Fix typo in SerialPortWrite()
The "read" word in SerialPortWrite() header comment block should be
"write".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18909 6f19259b-4bc3-4df7-8a09-765794883524
commit 5d7bc67e73c118b0a0f9a11e9ae933df19bedb05
Author: Star Zeng <star.zeng@intel.com>
Date: Fri Nov 20 01:49:48 2015 +0000
MdePkg SerialPortLib: Fix typo in SerialPortWrite()
The "read" word in SerialPortWrite() header comment block should be
"write".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18908 6f19259b-4bc3-4df7-8a09-765794883524
commit 41b474b78dd32e719daf686525e0ae7a431e3695
Author: Star Zeng <star.zeng@intel.com>
Date: Fri Nov 20 01:46:42 2015 +0000
MdePkg SerialIo.h: Fix typo "buts" to "bits"
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18907 6f19259b-4bc3-4df7-8a09-765794883524
commit 4ab4e20f1ade6a11824325b0d8529b0b1837d306
Author: Jeff Fan <jeff.fan@intel.com>
Date: Fri Nov 20 01:23:52 2015 +0000
UefiCpuPkg/SmmFeatureLib: Check SmmFeatureControl by Code_Access_Chk
Bit SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP is defined in SDM.
If set to 1 indicates that the SMM code access restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
If this bit is not set, we needn't to access register SmmFetureControl.
Otherwise, #GP exception may happen.
We need to check if SmmFeatureControl support or not by checking
SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP.
Because MSR_SMM_MCA_CAP is SMM-RO register, we should move this check from
SmmCpuFeaturesLibConstructor (non-SMM) to SmmCpuFeaturesInitializeProcessor
(SMM).
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18906 6f19259b-4bc3-4df7-8a09-765794883524
commit f6bc3a6d2623c317cefb990d4ae7cbcfc04008b9
Author: Jeff Fan <jeff.fan@intel.com>
Date: Fri Nov 20 01:22:00 2015 +0000
UefiCpuPkg: Not touch SmmFeatureControl if Code_Access_Chk not Set
Bit SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP is defined in SDM.
If set to 1 indicates that the SMM code access restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
If this bit is not set, we needn't to access register SmmFetureControl.
Otherwise, #GP exception may happen.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18905 6f19259b-4bc3-4df7-8a09-765794883524
commit d855b261d19e2c21c059293befe6ab37db1e8efb
Author: Mark Rutland <mark.rutland@arm.com>
Date: Thu Nov 19 14:39:48 2015 +0000
ArmPkg/ArmPlatformPkg: position vectors relative to base
We currently rely on .align directives to ensure that each exception
vector entry is the appropriate offset from the vector base address.
This is slightly fragile, as were an entry to become too large (greater
than 32 A64 instructions), all following entries would be silently
shifted until they meet the next alignment boundary. Thus we might
execute the wrong code in response to an exception.
To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org
directives to position each entry at the precise required offset from
the base of a vector. A vector entry which is too large will trigger a
build failure rather than a runtime failure which is difficult to debug.
For consistency, the base and end of each vector is similarly annotated,
with VECTOR_BASE and VECTOR_END, which provide the necessary alignment
and symbol exports. The now redundant directives and labels are removed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
commit fafb7e9c110eb89d1d1da18a822cae49758b76f6
Author: Mark Rutland <mark.rutland@arm.com>
Date: Thu Nov 19 14:14:25 2015 +0000
ArmPkg: correct TTBR1_EL1 settings in TCR_EL1
As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure
it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since
reset.
Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU
may make page table walks via TTBR1_EL1 at any time, potentially using
UNKNOWN values. This can result in a number of potential problems (e.g.
the CPU may load from MMIO registers as part of a page table walk).
Additionally, in the presence of Cortex-A57 erratum #822227, we must
program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value
of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a
hypervisor which makes use of PAR_EL1.
This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above
to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any
CPU capable of running EDK2 must support this granule, and given
TCR_EL1.EPD1, programming the field is not detrimental in the absence of
the erratum.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
commit 1a6f74d98887377bd5bb61484e54a3ac406f4a5d
Author: Cecil Sheng <cecil.sheng@hpe.com>
Date: Thu Nov 19 08:37:03 2015 +0000
ShellPkg: Corrected CatSPrint usage to prevent memory leaks.
CatSPrint allocates return buffer for the caller. The caller doesn't have to allocate one, and has to free the used buffers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18902 6f19259b-4bc3-4df7-8a09-765794883524
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