From: Platform Team regression test user <citrix-osstest@xenproject.org>
To: xen-devel@lists.xensource.com, osstest-admin@xenproject.org
Subject: [ovmf baseline-only test] 72116: all pass
Date: Sat, 16 Sep 2017 18:30:34 +0100 [thread overview]
Message-ID: <osstest-72116-mainreport@xen.org> (raw)
This run is configured for baseline tests only.
flight 72116 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/72116/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf b575ca32c8b05af5c23f46728ccf4937f2889ba8
baseline version:
ovmf 2f16993c255ca27bd3e8fa42489e8395d5308c3b
Last test of basis 72113 2017-09-16 05:19:59 Z 0 days
Testing same since 72116 2017-09-16 15:17:09 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Jiewen Yao <jiewen.yao@intel.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Push not applicable.
------------------------------------------------------------
commit b575ca32c8b05af5c23f46728ccf4937f2889ba8
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Thu Sep 7 16:06:27 2017 +0800
MdeModulePkg/XhciPei: Support IoMmu.
Update XHCI driver to consume IOMMU_PPI to allocate DMA buffer.
If no IOMMU_PPI exists, this driver still calls PEI service
to allocate DMA buffer, with assumption that DRAM==DMA.
This is a compatible change.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 8a4ed1188b7d3e6d39c9759a6f91fbbc5660160e
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Wed Sep 6 20:40:37 2017 +0800
IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 53269009cbe4bb59520630aef971b89f82a3c72d
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Wed Sep 6 20:40:24 2017 +0800
IntelSiliconPkg: Add PlatformVTdInfoSamplePei.
This is a sample driver to produce VTD_INFO PPI.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 71cfa709ed591ceca36017e93304cce1de51c810
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Fri Sep 1 16:31:12 2017 +0800
IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 3f5ed3fa13c66d66e1a7c5df9a78311f9a0ed991
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Fri Sep 1 16:30:46 2017 +0800
IntelSiliconPkg: Add IntelVTdPmrPei.
This PEIM is to produce IOMMU_PPI, so that PEI device
driver can have better DAM management.
This PEIM will setup VTD PMR register to protect
most DRAM. It allocates a big chunk DMA buffer in
the entrypoint, and only use this buffer for DMA.
Any other region is DMA protected.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 0b7df50021b9d21c2acef3bc06c683febbbeb60d
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Wed Sep 6 15:48:59 2017 +0800
IntelSiliconPkg/dec: Add VTD_INFO PPI GUID
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 77562d13ac7fa2c3840ccae598b26e665251ede7
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Wed Sep 6 15:47:23 2017 +0800
IntelSiliconPkg/include: Add VTD_INFO PPI.
This VTD_INFO_PPI is to provide VTD information in PEI.
As such, we can have a generic VTd driver.
It is a lightweight version DMAR table, but it does
not contain PCI device information.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit ffe77707a320077373d35029ba5b43253da6fd05
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Fri Sep 8 13:39:43 2017 +0800
IntelSiliconPkg/VTdDxe: Disable PMR
When VTd translation is enabled, PMR can be disable.
Or the DMA will be blocked by PMR.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 40cc2270556ec5e49d184c946bb58981f7155cf3
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Mon Sep 4 10:14:54 2017 +0800
IntelSiliconPkg/Vtd.h: Add definition for PMR.
Add missing PMR definition in VTd spec.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 915a3a82e017a3c098271bddffc1bb5352435ca5
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Fri Sep 1 16:31:00 2017 +0800
MdeModulePkg/Dec: Add IOMMU_PPI GUID.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
commit 2b620ee1ffc2c51ce9a63ada1039d1cf8c96ad7a
Author: Jiewen Yao <jiewen.yao@intel.com>
Date: Fri Sep 1 12:42:54 2017 +0800
MdeModulePkg/Include: Add IOMMU_PPI.
This IOMMU_PPI is to provide IOMMU abstraction in PEI.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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