[ovmf baseline-only test] 74901: all pass

[Platform Team regression test user <citrix-osstest@xenproject.org>]

This run is configured for baseline tests only.

flight 74901 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/74901/

Perfect :-)
All tests in this flight passed as required
version targeted for testing:
 ovmf                 8e586296c114f630188cfe4c76df91a1e2b7a5b2
baseline version:
 ovmf                 855abe0204cb932c8059a573a06a59ddc714ca49

Last test of basis    74894  2018-06-21 13:20:08 Z    1 days
Testing same since    74901  2018-06-22 18:52:42 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Ard Biesheuvel <ard.biesheuvel@linaro.org>
  Chris Co <Christopher.Co@microsoft.com>
  Christopher Co <christopher.co@microsoft.com>
  Dandan Bi <dandan.bi@intel.com>
  Fu Siyuan <siyuan.fu@intel.com>
  Ruiyu Ni <ruiyu.ni@intel.com>
  Sami Mujawar <sami.mujawar@arm.com>
  Sivaraman Nainar <sivaramann@amiindia.co.in>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 8e586296c114f630188cfe4c76df91a1e2b7a5b2
Author: Chris Co <Christopher.Co@microsoft.com>
Date:   Fri Apr 13 23:43:27 2018 +0000

    ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead of table base
    
    Mva address calculation should use the left-shifted current
    section index instead of the left-shifted table base address.
    
    Using the table base address here has the side-effect of potentially
    causing an access violation depending on the base address value.
    
    Cc: Leif Lindholm <leif.lindholm@linaro.org>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Christopher Co <christopher.co@microsoft.com>
    Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

commit 6e275c613e15ffc6dc79901fb244e8cb20af9948
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Thu Jun 21 09:17:52 2018 +0200

    ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory
    
    Given that these days, our ARM port only supports ARMv7 and later, we
    can assume that the page table walker's memory accesses are cache
    coherent, and so there is no need to perform cache maintenance. It
    does require the page tables themselves to reside in memory mapped as
    writeback cacheable so ASSERT() that this is the case.
    
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

commit 713aea34864ce5fc0a248b85bf3caa64fcf22467
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Wed Jun 20 21:01:52 2018 +0200

    ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contents
    
    Peculiarly enough, the current page table manipulation code takes it
    upon itself to write back and invalidate the memory contents covered
    by page and section mappings when their memory attributes change. It
    is not generally the case that data must be written back when such a
    change occurs, even when switching from cacheable to non-cacheable
    attributes, and in some cases, it is actually causing problems. (The
    cache maintenance is also performed on the PCIe MMIO regions as they
    get mapped by the PCI bus driver, and under virtualization, each
    cache maintenance operation on an emulated MMIO region triggers a
    round trip to the host and back)
    
    So let's just drop this code.
    
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

commit c2d6e2bc12b2a4e99304a1ebbc3474638721f5a8
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Thu Jun 14 13:55:21 2018 +0800

    ShellPkg/comp: return NOT_EQUAL when compared files are different
    
    Today's implementation returns 0 even when compared files are
    different.
    The patch returns 27 (SHELL_NOT_QUAL) in such case to follow
    the shell spec.
    
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>

commit 2e1083038d9aa74fcaa2db8158fdee7c8b4af3bb
Author: Dandan Bi <dandan.bi@intel.com>
Date:   Tue Jun 19 15:38:47 2018 +0800

    SignedCapsulePkg/SystemFirmwareUpdateDxe: Fix ECC issues
    
    Make function comments align with functions.
    
    Cc: Star Zeng <star.zeng@intel.com>
    Cc: Michael D Kinney <michael.d.kinney@intel.com>
    Cc: Jiewen Yao <jiewen.yao@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Dandan Bi <dandan.bi@intel.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

commit 24fee0528c32b240720547afdd737ca928b34e60
Author: Sami Mujawar <sami.mujawar@arm.com>
Date:   Tue Jun 19 19:58:14 2018 +0800

    MdeModulePkg: Enable SATA Controller PCI mem space
    
    The SATA controller driver crashes while accessing the
    PCI memory [AHCI Base Registers (ABAR)], as the PCI memory
    space is not enabled.
    
    Enable the PCI memory space access to prevent the SATA
    Controller driver from crashing.
    
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

commit 1e0db7b11987d0ec93be7dfe26102a327860fdbd
Author: Fu Siyuan <siyuan.fu@intel.com>
Date:   Thu Jun 14 10:30:09 2018 +0800

    MdeModulePkg/NetworkPkg: Checking for NULL pointer before use.
    
    Contributed-under: TianoCore Contribution Agreement 1.1
    
    Signed-off-by: Sivaraman Nainar <sivaramann@amiindia.co.in>
    Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>

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