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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0A2RrhERy4m0wqnhv+yzr75KOoszyNh2GvOlD1W08MjHu26KcRhi3xj/E2oo5UQiwlFpe/aobF2ghyxzk8E25hljsRmm95ZryEJk4EyFXH7iG+EmErigJlTzFYBQYm0DTnvhkWhdVmHDet/cUe8e5fhit4DtEI0wPCVmPofqXk993ETFNPYDKXTZACmaIP44PyVenLNurTjsjsFWPLDUb00tZZ0edYLatEKO90povVycqJvD4oHjz58/f9qMJcUVpWqyITlvXX+aebLj3PZfGqqUXF0ZL0wB0hcUSsZgHj4ebXwDy6oUl5mjw+k3XK1BOIRzh1LmacBj+AdP3hYW06JhRbbHL5WrVUIeuksUCrdT0bquXDKGo8VoOX8whpJusO3rRVoRa8OnbnGTLpZkhj4DtfKG3V0UiEgMnwVDcaQYgcCK6dHWkRDICaebTRoN X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 14:15:39.2940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22527333-68b8-4e02-73af-08df2b8ff493 X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: MI3PEPF0000848F.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR02MB8620 On Mon, Oct 12, 2026 at 17:31 +0200 Konrad Dybcio wrote: > On 10/2/26 12:36 AM, Waqar Hameed wrote: >> Multiple property data on a newline should be aligned with the first >> one. Found/fixed with dtfmt (Devicetree Source formatter). >> >> Signed-off-by: Waqar Hameed >> --- >> arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi >> index 346aef4a1d9f5..ac18744b50924 100644 >> --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi >> +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi >> @@ -1483,12 +1483,12 @@ cpu_crit1: trip1 { >> timer { >> compatible = "arm,armv7-timer"; >> interrupts = > - (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> > - (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> > - (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, >> > - (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; >> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; >> }; > > Likewise, these fit into 100c Yup, will change if we come to a conclusion (c.f. response in patch 19 and 22).