From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87387C433DB for ; Thu, 25 Mar 2021 16:39:51 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B30B61A25 for ; Thu, 25 Mar 2021 16:39:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4B30B61A25 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 8F05615E5; Thu, 25 Mar 2021 17:38:58 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 8F05615E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1616690388; bh=9lAFDvnSQJdI6yI+0TUmdQzyLp5NnTzx4cCSMTiBfZs=; h=Date:From:To:Subject:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jT1oe4eb18oY76KTsy7ReexQKyJzNokyIviVvrQsNfb7kgWguSVK6Kt5+veHiTNKg eXhIVt1bBVvZdgKFbCwtjUTO/IIzwiUX5/bOtsW4RTc8yr/tUBSlyuweMTWfZxJ56P Yc7DGV8hdSVSxlAP1WAfbGCWz1zLN02Glx+Cqf1M= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 19103F80257; Thu, 25 Mar 2021 17:38:58 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id D097AF8025F; Thu, 25 Mar 2021 17:38:55 +0100 (CET) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id E4076F80103 for ; Thu, 25 Mar 2021 17:38:52 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz E4076F80103 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id E55A2AC16; Thu, 25 Mar 2021 16:38:51 +0000 (UTC) Date: Thu, 25 Mar 2021 17:38:51 +0100 Message-ID: From: Takashi Iwai To: Andrey Grodzovsky Subject: Re: Adding movable PCIe BARs support in snd_hda_intel In-Reply-To: References: <30b36220-ff0f-d04c-1fca-349b3ff3a19b@amd.com> <9758cd4c-1246-a4ab-74eb-0e060248a00b@amd.com> <06b2dae2-a5ea-0cc8-891f-2aaff64ae260@amd.com> <65039cab-5561-aa9c-f270-8fa968a78f42@amd.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/25.3 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Cc: "Alexander.Deucher@amd.com" , alsa-devel@alsa-project.org, Sergei Miroshnichenko , "Christian.Koenig@amd.com" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Thu, 25 Mar 2021 17:13:41 +0100, Andrey Grodzovsky wrote: > > > > On 2021-03-25 2:58 a.m., Takashi Iwai wrote: > > On Wed, 24 Mar 2021 22:43:24 +0100, > > Andrey Grodzovsky wrote: > >> > >> Few comments - > >> > >> 1) Why we don't use snd_power_wait_and_ref in patch 3 in the common > >> handler ? > >> Don't we want the PCI rescan sequence to 'wait for' any in flight > >> taks that might be accessing registers and not only read/write/tlv > >> accesses ? > > > > Right, we don't need to block all ioctls, but only the ones that may > > access the hardware. So basically the patches 3-5 can be dropped if > > we take the patch 6. The current patch was written on top of the > > previous series, that's why it has both. > > > >> 2) Possible deadlock - > >> In azx_rescan_prepare - you put the card into SNDRV_CTL_POWER_D3hot > >> first and then 'wait for' all in flight tasks with the refcount. > >> The in flight tasks on the other hand, using snd_power_wait_and_ref, > >> may have already bumped up the refcount and now 'wait for' the card > >> to go into SNDRV_CTL_POWER_D0 which can't happen since PCI rescan > >> waits for the refocunt to drop to 0 before proceeding. > >> > >> Instead of snd_power_wait_and_ref can't we just call snd_power_ref > >> in common IOCTL before checking for power_state != SNDRV_CTL_POWER_D0 ? > >> Or is it because you don't want to fail IOCTLs ? > > > > No, this is the intended behavior and should work as-is because > > snd_power_wait_and_ref() drops the refcount in the loop before > > sleeping. The inc before the state check is a must for covering the > > possible race, and ditto for changing the power_state to D3hot before > > syncing. > > Ohh, missed the refcount dec in the wait loop... My bad. > > On boot the latest patch-set was throwing refcount warnings since > u are not supposed to inc from zerro count and so I fixed > with the attached patch. That way seems to work fine. Ah, I completely forgot about the oddness of refcount_t. Then I guess it's simpler to replace with atomic_*() instead. thanks, Takashi