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From: Andrew Gaylard <ag@ffroot.co.za>
To: Brian Masney <bmasney@redhat.com>
Cc: linux-clk@vger.kernel.org,  qinjian@cqplus1.com,
	mturquette@baylibre.com,  sboyd@kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] clk: sp7021: fix infrastructure clocks clobbering PLL provider entries
Date: Thu, 01 Oct 2026 09:39:40 +0200	[thread overview]
Message-ID: <sa6qzi9x41v.fsf@dev-ag> (raw)
In-Reply-To: <179069997903.213266.2923932929883625249.b4-reply@b4> (Brian Masney's message of "Tue, 29 Sep 2026 12:39:39 -0400")

Brian Masney <bmasney@redhat.com> writes:

> Hi Andrew,
>
> On 2026-08-20 15:02 +0200, Andrew Gaylard wrote:
>> The sp_clk_gates[] array previously included 9 infrastructure gate
>> clocks (CLK_SYSTEM, CLK_IOCTL, etc.) appended after the 64 DT-visible
>> gate clocks. The registration loop used the array index directly as the
>> hws[] index, so infrastructure clocks at positions 64-72 overwrote
>> hws[PLL_A] through hws[PLL_SYS].
[...]
>
> This patch does not apply against the tree.
>
> Brian

Hi Brian,

Thanks for looking at this path. I have a better fix now, but it needs
another series [0] to land first.

[0] https://lore.kernel.org/linux-arm-kernel/20260924164922.117236-1-ag@ffroot.co.za/

-- 
Andrew


      reply	other threads:[~2026-10-01  7:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 13:02 [PATCH] clk: sp7021: fix infrastructure clocks clobbering PLL provider entries Andrew Gaylard
2026-09-29 16:39 ` Brian Masney
2026-10-01  7:39   ` Andrew Gaylard [this message]

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