Re: [PATCH v4 1/2] PCI/LMR: Add Lane Margining at the Receiver debugfs interface

[sashiko-bot@kernel.org]

> Lane Margining at the Receiver moves the sampling point of a receiver
> away from its normal setting, in time or in voltage, while the link
> stays up, and reports the errors the receiver sees.  It is available
> on links running at 16.0 GT/s or faster, through the Lane Margining at
> the Receiver Extended Capability.
> 
> Add a debugfs directory, pcie_lmr_<device>, for each Downstream Port
> and each Function 0 below a Downstream Port that has the capability.
> 
> Writing 1 to 'enable' starts a margining session on the link.  ASPM is
> turned off with pci_disable_link_state(), Hardware Autonomous Width
> Disable and Hardware Autonomous Speed Disable are set on both ends,
> both ends are kept runtime resumed, and the port's Margining Ready bit
> is awaited.  Writing 0, or removing either end of the link, ends the
> session and undoes these steps.  Only one session can be active on a
> link.
> 
> During a session, 'receiver' selects the receiver, laneN/margin_timing
> and laneN/margin_voltage issue Step Margin commands, laneN/caps shows
> the parameters the receiver reports, and laneN/status shows the
> response to the last step command, including the error count.  Before
> each command, the link is checked against the state the session
> started in: speed, width, Margining Ready, ASPM still off, and no
> system suspend since.
> 
> The kernel does not run margining sweeps or interpret the results;
> that is left to user space.
> 
> Signed-off-by: Priyank Rathod <rathodpriyank@google.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20261006-pcie-link-endpoints-v4-0-ad5398c4260c@google.com?part=1