From: sashiko-bot@kernel.org
To: "David Zhang" <yidong.zhang@amd.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support
Date: Fri, 09 Oct 2026 23:08:32 +0000 [thread overview]
Message-ID: <sashiko-outbox-166175@kernel.org> (raw)
In-Reply-To: <20261009225343.3079074-6-yidong.zhang@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] amdxdna: user-triggerable WARN_ON via AMDXDNA_BO_DEV_HEAP on NPU3 classic
--
commit 9daa4537d3513c6a4bc057f8afd01b65162be2b6
Author: David Zhang <yidong.zhang@amd.com>
accel/amdxdna: Add NPU3 classic device support
Add NPU3 classic device operations (aie4_classic_ops) and register
definitions, as well as the PCI device ID and firmware declarations for
NPU3 classic devices. Remove device IDs 0x1B0B and 0x1B0C because those
devices will not be released.
> diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c
> index 93f749acb5d5d..c82433d629012 100644
> --- a/drivers/accel/amdxdna/npu3_regs.c
> +++ b/drivers/accel/amdxdna/npu3_regs.c
> @@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = {
> .cert_feature_tbl = npu3_cert_feature_table,
> .ops = &aie4_vf_ops,
> };
> +
> +const struct amdxdna_dev_info dev_npu3_classic_info = {
> + .mbox_bar = NPU3_MBOX_BAR,
> + .sram_bar = NPU3_MBOX_BUFFER_BAR,
> + .psp_bar = NPU3_PSP_BAR_INDEX,
> + .smu_bar = NPU3_SMU_BAR_INDEX,
> + .doorbell_bar = NPU3_DOORBELL_BAR,
> + .default_vbnv = "RyzenAI-npu3",
> + .device_type = AMDXDNA_DEV_TYPE_UMQ,
> + .dev_priv = &npu3_dev_priv,
> + .fw_feature_tbl = npu3_fw_feature_table,
> + .cert_feature_tbl = npu3_cert_feature_table,
> + .ops = &aie4_classic_ops,
> +};
[Severity: Medium]
Since dev_mem_size is omitted here, it defaults to 0. Does this cause a
kernel warning when creating a device heap BO?
If an unprivileged user opens the accelerator device and requests a BO with
type AMDXDNA_BO_DEV_HEAP, the ioctl dispatcher calls
amdxdna_drm_create_dev_heap_bo() which unconditionally evaluates:
WARN_ON(!is_power_of_2(xdna->dev_info->dev_mem_size));
Since dev_mem_size is 0, this will evaluate to true and trigger a warning,
potentially causing a local denial of service if panic_on_warn is enabled.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009225343.3079074-1-yidong.zhang@amd.com?part=5
next prev parent reply other threads:[~2026-10-09 23:08 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 22:53 [PATCH V4 00/19] accel/amdxdna: Kernel submission and PM for AIE4 David Zhang
2026-10-09 22:53 ` [PATCH V4 01/19] accel/amdxdna: Rename NPU3 firmware files David Zhang
2026-10-09 22:53 ` [PATCH V4 02/19] accel/amdxdna: Remove mmap for doorbell David Zhang
2026-10-12 20:37 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 03/19] accel/amdxdna: Add CERT firmware version support David Zhang
2026-10-12 20:39 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 04/19] accel/amdxdna: Support firmware 6.0 David Zhang
2026-10-09 23:08 ` sashiko-bot
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 05/19] accel/amdxdna: Add NPU3 classic device support David Zhang
2026-10-09 23:08 ` sashiko-bot [this message]
2026-10-12 20:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 06/19] accel/amdxdna: Add AIE version query to aie4_get_info David Zhang
2026-10-12 20:55 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 07/19] accel/amdxdna: Add get and set power_mode for AIE4 David Zhang
2026-10-12 21:29 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 08/19] accel/amdxdna: Add clock, DPM frequency, and resource info queries " David Zhang
2026-10-09 23:12 ` sashiko-bot
2026-10-12 22:58 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 09/19] accel/amdxdna: Add context switch hysteresis with debugfs control David Zhang
2026-10-13 18:29 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence David Zhang
2026-10-13 18:33 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 11/19] accel/amdxdna: Decouple AIE4 doorbell and MSI-X notify transport hooks David Zhang
2026-10-13 18:38 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 12/19] accel/amdxdna: Implement AIE4 kernel queue lifecycle and memory layout David Zhang
2026-10-13 18:41 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 13/19] accel/amdxdna: Prepare for AIE4 command submission David Zhang
2026-10-13 18:42 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 14/19] accel/amdxdna: Move HMM invalidate wait into common GEM code David Zhang
2026-10-13 18:45 ` Lizhi Hou
2026-10-09 22:53 ` [PATCH V4 15/19] accel/amdxdna: Make populate_range common for AIE2 and AIE4 David Zhang
2026-10-09 23:06 ` sashiko-bot
2026-10-09 22:53 ` [PATCH V4 16/19] accel/amdxdna: Implement AIE4 command packet building and submission David Zhang
2026-10-09 22:53 ` [PATCH V4 17/19] accel/amdxdna: Enable AIE4 firmware logging to DRAM David Zhang
2026-10-09 23:14 ` sashiko-bot
2026-10-09 22:53 ` [PATCH V4 18/19] accel/amdxdna: Implement AIE4 suspend and resume David Zhang
2026-10-09 22:53 ` [PATCH V4 19/19] accel/amdxdna: Implement runtime suspend and resume support David Zhang
2026-10-09 23:17 ` sashiko-bot
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