Re: [PATCH v3 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dts: incorrect RGMII phy-mode causes double clock delay
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commit 471320732fb47362c8b5d5e16472052117a95204
Author: Jia Wang <wangjia@ultrarisc.com>

riscv: dts: ultrarisc: Add Milk-V Titan board device tree

This commit introduces the device tree for the Milk-V Titan board, an ITX
motherboard based on the UltraRISC DP1000 SoC.

Link: https://milkv.io/docs/titan/overview

> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts
> new file mode 100644
> index 0000000000000..59edd8157221a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts

[ ... ]

> +&ethernet {
> +	phy-handle = <&phy0>;
> +	/*
> +	 * The PCB does not add RGMII TX or RX clock delays. The DP1000
> +	 * integration adds fixed delays in both directions.
> +	 */
> +	phy-mode = "rgmii-id";

[Severity: Medium]
The comment notes that the DP1000 integration already adds fixed delays in
both directions. When the MAC or SoC natively provides the RGMII delays,
shouldn't phy-mode be set to "rgmii" instead of "rgmii-id"?

Setting it to "rgmii-id" instructs the PHY to insert its own internal delays
as well, which might result in a double-delayed link. This combination could
shift the clock outside the valid data window, leading to link failures or
dropped packets.

> +
> +	status = "okay";
> +

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Sashiko AI review · https://sashiko.dev/#/patchset/20261013-ultrarisc-dts-v3-0-5ff3ebb2a90d@ultrarisc.com?part=7