Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: missing maxItems constraint for supported-frequencies-hz
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commit 6b7fe4cd90d007b210798a0e52bd9d32e38cab03
Author: Ali Rouhi <arouhi@sitime.com>

dt-bindings: dpll: add SiTime SiT95316 clock generator

This commit adds device tree bindings for the SiTime SiT9531x family of
clock generators. These are I2C-controlled programmable clock generators
with integrated DPLL functionality.

> diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml

[ ... ]

> +  input-pins:
> +    type: object
> +    patternProperties:
> +      "^pin@[0-9a-f]+$":
> +        type: object
> +        properties:
> +          reg:
> +            maximum: 7
> +
> +          supported-frequencies-hz:
> +            description:
> +              The rate wired to the input, in Hz, as a single entry.  An
> +              input runs at the rate the board feeds it and has no
> +              frequency to select, so that entry is what the pin reports
> +              as its frequency.

[Severity: Low]
The description states this must be a single entry, but should there be a
maxItems: 1 constraint to structurally enforce this? Without it, a device
tree node providing an array of multiple 64-bit frequencies for an input pin
will silently pass schema validation.

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20261013224131.27149-1-arouhi@sitime.com?part=2