Re: [PATCH 2/2] serial: sifive: avoid division by zero in the clock notifier

[sashiko-bot@kernel.org]

> From: Sebastian Alba <sebasjosue84@estudiantec.cr>
> 
> sifive_serial_probe() registers the clock rate-change notifier before
> it initialises the two fields that notifier divides by.  ssp comes from
> devm_kzalloc(), so between clk_notifier_register() and the assignments
> a few lines below, both ssp->baud_rate and ssp->port.uartclk are zero.
> 
> A rate change taken in that window reaches:
> 
>   PRE_RATE_CHANGE:  udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate))
>   POST_RATE_CHANGE: __ssp_update_div() ->
>                       DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1
> 
> On RISC-V an integer division by zero does not trap; the ISA defines the
> result as all bits set.  DIV_ROUND_UP() therefore yields ULONG_MAX and
> udelay() busy-waits essentially forever, hanging the CPU, rather than
> producing a clean oops.  The POST_RATE_CHANGE path additionally programs
> a bogus divisor into the hardware.
> 
> On the FU740 the UART clock is derived from the CPU clock through a
> synchronous divide-by-two, as the notifier's own comment describes, so
> any CPU rate change during probe can hit this.
> 
> Initialise uartclk and baud_rate before registering the notifier, and
> bail out early if the notifier is ever called with no baud rate set.
> 
> Fixes: 45c054d0815b ("tty: serial: add driver for the SiFive UART")
> Signed-off-by: Sebastian Alba <sebasjosue84@estudiantec.cr>

Sashiko has reviewed this patch and found no issues.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261017074453.62645-1-sebasjosue84@gmail.com?part=2