Re: [PATCH net-next v3 5/9] net: stmmac: mediatek: add RX/TX delay stage divider in platform data

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] net: stmmac: mediatek: copy-paste error assigns RMII macro to RGMII TX delay divider
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commit c43e3615c53c38caf38fb0fc788d29a2ffa994ad
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

    net: stmmac: mediatek: add RX/TX delay stage divider in platform data

This commit adds RX and TX delay stage divider values to the variant
platform data for MediaTek SoCs. This prepares the driver for newer SoCs
like MT8189 which have different internal delay stage steps.

> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> index 596411d4a5b2b..cb5bda53edb94 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

[ ... ]

> @@ -258,6 +270,10 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
>  	.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
>  	.rx_delay_max = MT2712_RGMII_DLY_RXC_MAX,
>  	.tx_delay_max = MT2712_RGMII_DLY_TXC_MAX,
> +	.rx_rmii_delay_stage_div = MT2712_RMII_DLY_RXC_STAGE_DIV,
> +	.tx_rmii_delay_stage_div = MT2712_RMII_DLY_TXC_STAGE_DIV,
> +	.rx_rgmii_delay_stage_div = MT2712_RGMII_DLY_RXC_STAGE_DIV,
> +	.tx_rgmii_delay_stage_div = MT2712_RMII_DLY_TXC_STAGE_DIV,
                                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: High]
Does this initialization assign the wrong macro for the RGMII TX delay divider?

It looks like mt2712_gmac_variant.tx_rgmii_delay_stage_div is being initialized
with the MT2712_RMII_DLY_TXC_STAGE_DIV macro instead of the RGMII variant due
to a possible copy-paste error.

Before this patch, mt2712_set_delay() correctly used the RGMII constant for
the tx_delay_stage_div. Because of this error, when configuring the TX delay
for an RGMII interface on the MT2712 platform, the driver will now divide the
delay by the RMII constant instead.

This will result in an incorrect, much larger delay stage value being
programmed into the PERI_ETH_DLY register via the ETH_DLY_GTXC_STAGES field,
which could break RGMII transmission timing.

>  	.dma_bit_mask = 33,
>  };

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Sashiko AI review · https://sashiko.dev/#/patchset/20261016-dwmac-mediatek-mt8189-v3-0-25daf2bbcf35@collabora.com?part=5