Re: [PATCH v5 6/8] irqchip/realtek-rtd1319d: Add driver for Realtek RTD1319D and RTD1325 SoCs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] irqchip/realtek-rtd1319d: unreachable DRTC IRQs excluded from subset masks
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commit e59f4cebdbdec34b9436dc4ae09a46cfa2ab3770
Author: James Tai <james.tai@realtek.com>

irqchip/realtek-rtd1319d: Add driver for Realtek RTD1319D and RTD1325 SoCs

This commit adds support for the ISO and MISC interrupt controllers on Realtek
DHC RTD1319D and RTD1325 SoCs.

> diff --git a/drivers/irqchip/irq-realtek-rtd1319d.c b/drivers/irqchip/irq-realtek-rtd1319d.c
> new file mode 100644
> index 0000000000000..4bac12c02cbe2
> --- /dev/null
> +++ b/drivers/irqchip/irq-realtek-rtd1319d.c
> @@ -0,0 +1,197 @@

[ ... ]

> +#define ISO_NMI_WDT_MASK	0x08008090
> +#define ISO_NORMAL_MASK		0xf7ff7f6e
> +#define MISC_NORMAL_MASK	0xffe0ded6
> +#define MISC_UART1_MASK		0x00000028
> +#define MISC_UART2_MASK		0x00002100

[ ... ]

> +enum rtd1319d_misc_isr_bits {
> +	RTD1319D_MISC_ISR_UR1_SHIFT		= 3,
> +	RTD1319D_MISC_ISR_TC5_SHIFT		= 4,
> +	RTD1319D_MISC_ISR_UR1_TO_SHIFT		= 5,
> +	RTD1319D_MISC_ISR_TC0_SHIFT		= 6,
> +	RTD1319D_MISC_ISR_TC1_SHIFT		= 7,
> +	RTD1319D_MISC_ISR_UR2_SHIFT		= 8,
> +	RTD1319D_MISC_ISR_UR2_TO_SHIFT		= 13,
> +	RTD1319D_MISC_ISR_I2C5_SHIFT		= 14,
> +	RTD1319D_MISC_ISR_I2C4_SHIFT		= 15,
> +	RTD1319D_MISC_ISR_DRTC_HSEC_SHIFT	= 16,
> +	RTD1319D_MISC_ISR_DRTC_MIN_SHIFT	= 17,
> +	RTD1319D_MISC_ISR_DRTC_HOUR_SHIFT	= 18,
> +	RTD1319D_MISC_ISR_DRTC_DATE_SHIFT	= 19,
> +	RTD1319D_MISC_ISR_DRTC_ALARM_SHIFT	= 20,
> +	RTD1319D_MISC_ISR_I2C3_SHIFT		= 23,
> +	RTD1319D_MISC_ISR_SC0_SHIFT		= 24,
> +	RTD1319D_MISC_ISR_SC1_SHIFT		= 25,
> +	RTD1319D_MISC_ISR_SPI_SHIFT		= 27,
> +	RTD1319D_MISC_ISR_FAN_SHIFT		= 29,
> +};
> +
> +static const u32 rtd1319d_misc_isr_to_scpu_int_en_mask[32] = {
> +	[RTD1319D_MISC_ISR_UR1_SHIFT]		= BIT(3),
> +	[RTD1319D_MISC_ISR_UR1_TO_SHIFT]	= BIT(5),
> +	[RTD1319D_MISC_ISR_UR2_TO_SHIFT]	= BIT(6),
> +	[RTD1319D_MISC_ISR_UR2_SHIFT]		= BIT(7),
> +	[RTD1319D_MISC_ISR_I2C5_SHIFT]		= BIT(14),
> +	[RTD1319D_MISC_ISR_I2C4_SHIFT]		= BIT(15),
> +	[RTD1319D_MISC_ISR_DRTC_HSEC_SHIFT]	= BIT(16),
> +	[RTD1319D_MISC_ISR_DRTC_MIN_SHIFT]	= BIT(17),
> +	[RTD1319D_MISC_ISR_DRTC_HOUR_SHIFT]	= BIT(18),
> +	[RTD1319D_MISC_ISR_DRTC_DATE_SHIFT]	= BIT(19),
> +	[RTD1319D_MISC_ISR_DRTC_ALARM_SHIFT]	= BIT(20),
> +	[RTD1319D_MISC_ISR_SC0_SHIFT]		= BIT(24),
> +	[RTD1319D_MISC_ISR_SC1_SHIFT]		= BIT(25),
> +	[RTD1319D_MISC_ISR_SPI_SHIFT]		= BIT(27),
> +	[RTD1319D_MISC_ISR_I2C3_SHIFT]		= BIT(28),
> +	[RTD1319D_MISC_ISR_FAN_SHIFT]		= BIT(29),
> +};

[ ... ]

> +static const struct realtek_intc_mask rtd1319d_intc_misc_cfgs[] = {
> +	{ MISC_NORMAL_MASK, },
> +	{ MISC_UART1_MASK, },
> +	{ MISC_UART2_MASK, },
> +};

[Severity: Medium]
Are the DRTC interrupts (bits 16..20) intentionally excluded from
rtd1319d_intc_misc_cfgs[], or is a subset mask missing for them?

rtd1319d_misc_isr_to_scpu_int_en_mask[] defines enable masks for
RTD1319D_MISC_ISR_DRTC_HSEC_SHIFT through RTD1319D_MISC_ISR_DRTC_ALARM_SHIFT,
so realtek_intc_unmask_irq() will set BIT(16)..BIT(20) in MISC_ISR_EN_OFFSET
when a consumer enables one of those interrupts.

However, MISC_NORMAL_MASK (0xffe0ded6) clears bits 16..20 (0x001f0000), and
neither MISC_UART1_MASK (0x00000028) nor MISC_UART2_MASK (0x00002100)
includes them. When a DRTC interrupt fires, realtek_intc_dispatch() filters
MISC_ISR_OFFSET by subset_data->subset_mask->ints_mask across
rtd1319d_intc_misc_cfgs[], so none of the subset handlers will dispatch or
clear those pending bits.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261018160653.3940371-1-eleanor.lin@realtek.com?part=6